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| Number | Title | Issue Date |
| 7628897 | Reactive ion etching for semiconductor device feature topography modification A film is deposited on a substrate disposed in a substrate processing chamber. The substrate has a trench formed between adjacent raised surfaces. A first portion of the film is deposited over the substrate from a first gaseous mixture flowed into the process chambe... | 12/08/2009 |
| 7399388 | Sequential gas flow oxide deposition technique A method of depositing a silica glass insulating film over a substrate. In one embodiment the method comprises exposing the substrate to a silicon-containing reactant introduced into a chamber in which the substrate is disposed such that one or more layers of the si... | 07/15/2008 |
| 7335611 | Copper conductor annealing process employing high speed optical annealing with a low temperature-deposited optical absorber layer A method of forming a conductor in a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier metal on... | 02/26/2008 |
| 7323401 | Semiconductor substrate process using a low temperature deposited carbon-containing hard mask A method of processing a thin film structure on a semiconductor substrate using an optically writable mask includes placing the substrate in a reactor chamber, the substrate having on its surface a target layer to be etched in accordance with a predetermined pattern... | 01/29/2008 |
| 7320734 | Plasma immersion ion implantation system including a plasma source having low dissociation and low minimum plasma voltage A system for processing a workpiece includes a plasma immersion ion implantation reactor with an enclosure having a side wall and a ceiling and defining a chamber, and a workpiece support pedestal within the chamber having a workpiece support surface facing the ceil... | 01/22/2008 |
| 7312148 | Copper barrier reflow process employing high speed optical annealing A method of forming a barrier layer for a thin film structure on a semiconductor substrate includes forming high aspect ratio openings in a base layer having vertical side walls, depositing a dielectric barrier layer comprising a dielectric compound of a barrier met... | 12/25/2007 |
| 7312162 | Low temperature plasma deposition process for carbon layer deposition A method of depositing a carbon layer on a workpiece includes placing the workpiece in a reactor chamber, introducing a carbon-containing process gas into the chamber, generating a reentrant toroidal RF plasma current in a reentrant path that includes a process zone... | 12/25/2007 |
| 7303982 | Plasma immersion ion implantation process using an inductively coupled plasma source having low dissociation and low minimum plasma voltage A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpi... | 12/04/2007 |
| 7294563 | Semiconductor on insulator vertical transistor fabrication and doping process A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conform... | 11/13/2007 |
| 7291546 | Method and apparatus for reducing charge loss in a nonvolatile memory cell A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate desi... | 11/06/2007 |
| 7291545 | Plasma immersion ion implantation process using a capacitively couple plasma source having low dissociation and low minimum plasma voltage A method of ion implanting a species in a workpiece to a selected ion implantation profile depth includes placing a workpiece having a semiconductor material on an electrostatic chuck in or near a processing region of a plasma reactor chamber and applying a chucking... | 11/06/2007 |
| 7292428 | Electrostatic chuck with smart lift-pin mechanism for a plasma reactor A lift pin assembly for use in a reactor for processing a workpiece includes plural lift pins extending generally parallel with a lift direction, each of the plural lift pins having a top end for supporting a workpiece and a bottom end. A lift table faces the bottom... | 11/06/2007 |
| 7288491 | Plasma immersion ion implantation process One method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber includes initially depositing a seasoning film on the interior surfaces of the plasma reactor chamber before the workpiece is introduced, by introducing a seasoning... | 10/30/2007 |
| 7270729 | System for, and method of, etching a surface on a wafer First and second electrodes and magnets between the electrodes define an enclosure. The first electrode is biased at a high voltage to produce a high intensity electrical field. The second electrode is biased at a low negative voltage by a low alternating voltage to... | 09/18/2007 |
| 7271467 | Multiple oxide thicknesses for merged memory and logic applications Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologi... | 09/18/2007 |
| 7238621 | Integrated optical MEMS devices A method for fabricating an optical device and micromechanical device, wherein both devices are monolithically-integrated with a substrate. The optical surfaces and micromechanical devices are each formed in an etch step that is well-suited for forming that device. ... | 07/03/2007 |
| 7223676 | Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer A low temperature process for depositing a coating containing any of silicon, nitrogen, hydrogen or oxygen on a workpiece includes placing the workpiece in a reactor chamber facing a processing region of the chamber, introducing a process gas containing any of silic... | 05/29/2007 |
| 7214609 | Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cav... | 05/08/2007 |
| 7205240 | HDP-CVD multistep gapfill process A gapfill process is provided using cycling of HDP-CVD deposition, etching, and deposition step. The fluent gas during the first deposition step includes an inert gas such as He, but includes H2 during the remainder deposition step. The higher average mol... | 04/17/2007 |
| 7183177 | Silicon-on-insulator wafer transfer method using surface activation plasma immersion ion implantation for wafer-to-wafer adhesion enhancement A method of fabricating a semiconductor-on-insulator structure from a pair of semiconductor wafers, includes forming an oxide layer on at least a first surface of a first one of the wafers and performing a bonding enhancement implantation step by ion implantation of... | 02/27/2007 |
| 7166200 | Method and apparatus for an improved upper electrode plate in a plasma processing system The present invention presents an improved upper electrode for a plasma processing system, wherein the design and fabrication of an electrode plate coupled to an upper assembly advantageously provides gas injection of a process gas with substantially minimal erosion... | 01/23/2007 |
| 7166524 | Method for ion implanting insulator material to reduce dielectric constant An integrated microelectronic circuit has a multi-layer interconnect structure overlying the transistors consisting of stacked metal pattern layers and insulating layers separating adjacent ones of said metal pattern layers. Each of the insulating layers is a dielec... | 01/23/2007 |
| 7150811 | Ion beam for target recovery A charged particle beam apparatus and method for locally removing material from a predetermined location on a workpiece, such as the removal of a metallization layer covering an alignment mark on a wafer. The invention is particularly suited for high-volume mass pro... | 12/19/2006 |
| 7137354 | Plasma immersion ion implantation apparatus including a plasma source having low dissociation and low minimum plasma voltage A plasma immersion ion implantation reactor for ion implanting a species into a surface layer of a workpiece includes an enclosure which has a side wall and a ceiling defining a chamber and a workpiece support pedestal within the chamber having a workpiece support s... | 11/21/2006 |
| 7122485 | Deposition profile modification through process chemistry Disclosed are methods for modifying the topography of HDP CVD films by modifying the composition of the reactive mixture. The methods allow for deposition profile control independent of film deposition rate. They rely on changes in the process chemistry of the HDP C... | 10/17/2006 |
| 7118992 | Wafer thinning using magnetic mirror plasma A method for manufacturing integrated circuits uses an atmospheric magnetic mirror plasma etching apparatus to thin a semiconductor wafer. In addition the process may, while thinning, both segregate and expose through-die vias for an integrated circuit chip. To segr... | 10/10/2006 |
| 7097886 | Deposition process for high aspect ratio trenches A method of depositing an insulating film over a substrate having a gap formed between two adjacent raised features. The method includes depositing one portion of the insulating film over the substrate and in the gap using a high density plasma process that has simu... | 08/29/2006 |
| 7094670 | Plasma immersion ion implantation process A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersi... | 08/22/2006 |
| 7094316 | Externally excited torroidal plasma source A plasma reactor for processing a workpiece, including an enclosure defining a vacuum chamber, a workpiece support within the enclosure facing an overlying portion of the enclosure, the enclosure having at least first and second openings therethrough near generally ... | 08/22/2006 |
| 7084477 | Semiconductor device and manufacturing method of the same To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embed... | 08/01/2006 |
| 7078282 | Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, ... | 07/18/2006 |
| 7067195 | Coatings having low emissivity and low solar reflectance The invention provides low solar reflectance, low-emissivity coatings. The invention provides a monolithic pane bearing a low solar reflectance, low-emissivity coating. Further, the invention provides an insulating glass unit bearing a low solar reflectance, low-emi... | 06/27/2006 |
| RE39143 | Method for making a wafer-pair having sealed chambers A method for fabricating a wafer-pair having at least one recess in one wafer and the recess formed into a chamber with the attaching of the other wafer which has a port plugged with a deposited layer on its external surface. The deposition of the layer may be perfo... | 06/27/2006 |
| 7067440 | Gap fill for high aspect ratio structures Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process invol... | 06/27/2006 |
| 7053002 | Plasma preclean with argon, helium, and hydrogen gases The present invention provides a method and apparatus for precleaning a patterned substrate with a plasma comprising a mixture of argon, helium, and hydrogen. Addition of helium to the gas mixture of argon and hydrogen surprisingly increases the etch rate in compari... | 05/30/2006 |
| 7052971 | Method for manufacturing semiconductor device A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position low... | 05/30/2006 |
| 7049169 | Method of fabricating a semiconductor device According to the present invention, by applying a basic surface-processing agent to a film underlying a resist, the excessive photoacid present at the interface between the resist and the front-end film is neutralized and the pattern shape can be controlled. The pre... | 05/23/2006 |
| 7037813 | Plasma immersion ion implantation process using a capacitively coupled plasma source having low dissociation and low minimum plasma voltage A method for implanting ions in a surface layer of a workpiece includes placing the workpiece on a workpiece support in a chamber with the surface layer being in facing relationship with a ceiling of the chamber, thereby defining a processing zone between the workpi... | 05/02/2006 |
| 7001854 | Hydrogen-based phosphosilicate glass process for gap fill of high aspect ratio structures Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.13 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process invol... | 02/21/2006 |
| 6975072 | Ion source with external RF antenna A radio frequency (RF) driven plasma ion source has an external RF antenna, i.e. the RF antenna is positioned outside the plasma generating chamber rather than inside. The RF antenna is typically formed of a small diameter metal tube coated with an insulator. An ext... | 12/13/2005 |
