Bizarre Patents
Method and apparatus for making a drink hop along a bar or counter
A method for generating a drink which appears to hop from a remote spot on the bar or counter and take one or more leaps, before landing in a patron's glass.
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| Number | Title | Issue Date |
| 7988794 | Semiconductor device and method A semiconductor device having a topology adjustment and a method for adjusting the topology of a semiconductor device. The semiconductor device includes a semiconductor wafer having first and second opposing sides with an active area formed on a first portion of the... | 08/02/2011 |
| 7727340 | Inclusion of nitrogen at the silicon dioxide-silicon carbide interface for passivation of interface defects In one aspect the present invention provides a method for manufacturing a silicon carbide semiconductor device. A layer of silicon dioxide is formed on a silicon carbide substrate and nitrogen is incorporated at the silicon dioxide/silicon carbide interface. In one ... | 06/01/2010 |
| 7655099 | High-k dielectric film, method of forming the same and related semiconductor device A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first ... | 02/02/2010 |
| 7578891 | Adhesive bonding sheet, semiconductor device using the same, and method for manufacturing such semiconductor device An adhesive bonding sheet having an optically transmitting supporting substrate and an adhesive bonding layer, and being used in both a dicing step and a semiconductor element adhesion step, wherein the adhesive bonding layer comprises: ... | 08/25/2009 |
| 7364958 | CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hyb... | 04/29/2008 |
| 7358191 | Method for decreasing sheet resistivity variations of an interconnect metal layer According to one exemplary embodiment, a method includes a step of forming a number of trenches in a dielectric layer, where the dielectric layer is situated over a wafer. The method further includes forming a metal layer over the dielectric layer and in the trenche... | 04/15/2008 |
| 7323411 | Method of selective tungsten deposition on a silicon surface In one embodiment, a selective tungsten deposition process includes the steps of pre-flowing silane into a deposition chamber, pumping down the chamber, and then selectively depositing tungsten on a silicon surface. The silane pre-flow helps minimize silicon consump... | 01/29/2008 |
| 7302982 | Label applicator and system A label applicator including a support surface having a central area and curving downwardly from the central area. A post assembly extends up from the central area such that a label having a label through-hole can be positioned in a support position generally on the... | 12/04/2007 |
| 7270724 | Scanning plasma reactor A scanning plasma reactor for exciting reactant gases at a substrate surface including a beam forming module, a gas injection module, a reaction chamber with a window and a vacuum chuck, a gas exhaust module. Radiation from the beam forming module and the reactant g... | 09/18/2007 |
| 7268440 | Fabrication of semiconductor integrated circuit chips A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of ac... | 09/11/2007 |
| 7259053 | Methods for forming a device isolation structure in a semiconductor device Methods of forming a device isolation structure in a semiconductor device are disclosed. A disclosed method comprises forming a p-type well and an n-type well in a semiconductor substrate; sequentially depositing a gate insulating layer and a gate electrode material... | 08/21/2007 |
| 7259073 | Semiconductor device and method of manufacturing the same A method of manufacturing a semiconductor device that suppresses emergence of a waste in an isolation trench formation process is to be provided. The method comprises forming an isolation trench having a predetermined depth from a surface of a semiconductor s... | 08/21/2007 |
| 7242012 | Lithography device for semiconductor circuit pattern generator General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 07/10/2007 |
| 7238609 | Method for fabricating semiconductor device A method for fabricating a semiconductor device has the steps of forming a conductive film on a substrate, forming an insulating film such that the conductive film is covered with the insulating film, forming, in the insulating film, a hole having a bottom portion n... | 07/03/2007 |
| 7235856 | Trench isolation for semiconductor devices In etching trench isolation structures, a pad oxide or sacrificial oxide may be formed with substantially the same (or higher) etch rate as the trench filler. Because the etch rate in the trench area is substantially similar to (or less than) the etch rate in the no... | 06/26/2007 |
| 7223696 | Methods for maskless lithography General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 05/29/2007 |
| 7193239 | Three dimensional structure integrated circuit A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 03/20/2007 |
| 7186349 | Fluid ejection device and method of fabricating the same A fluid ejection device includes a first substrate having a first crystal orientation, a second substrate having a second crystal orientation, bound to the first substrate, a manifold through the first and second substrates, a chamber formed in the second substrate,... | 03/06/2007 |
| 7187045 | Junction field effect metal oxide compound semiconductor integrated transistor devices A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor includes a gate insulating structure comprised of a first conducting oxide layer comprised of indium oxide compounds positioned immediately on top of the compound semiconducto... | 03/06/2007 |
| 7176545 | Apparatus and methods for maskless pattern generation General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor ... | 02/13/2007 |
| 7153757 | Method for direct bonding two silicon wafers for minimising interfacial oxide and stresses at the bond interface, and an SOI structure A semiconductor substrate (1) comprises first and second silicon wafers (2,3) directly bonded together with interfacial oxide and interfacial stresses minimised along a bond interface (5), which is defined by bond faces (7) of the first a... | 12/26/2006 |
| 7138295 | Method of information processing using three dimensional integrated circuits A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, red... | 11/21/2006 |
| 7115524 | Methods of processing a semiconductor substrate The invention includes methods of processing semiconductor substrates. In one implementation, a semiconductor substrate is provided which has an outer surface. Such surface has a peripheral region received about a peripheral edge of the semiconductor substrate. A la... | 10/03/2006 |
| 7102224 | Encapsulated component and method for the production thereof A component includes a chip having a first chip face and a second chip face, where the first chip face includes component structures and connector metallizations associated with the component structures. The component also includes a frame structure on the first chi... | 09/05/2006 |
| 7098148 | Method for heat treating a semiconductor wafer A method for heat treatment of a semiconductor wafer placed on a support. The method includes subjecting the wafer to a heat treatment with a slow temperature rise from an initial temperature to a treatment ending temperature, and minimizing slip lines that would ot... | 08/29/2006 |
| 7098544 | Edge seal for integrated circuit chips A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in th... | 08/29/2006 |
| 7064387 | Silicon-on-insulator (SOI) substrate and method for manufacturing the same A silicon-on-insulator (SOI) substrate includes a silicon substrate including an active region defined by a field region that surrounds the active region for device isolation. The field region includes a first oxygen-ion-injected isolation region and a second oxygen... | 06/20/2006 |
| 7052584 | Method of forming a capacitor A method of forming a capacitor having a capacitor dielectric layer comprising ABO3, where “A” is selected from the group consisting of Sn and Group IIA metal elements and mixtures thereof, where “B” is selected from the group consisting of Group ... | 05/30/2006 |
| 7052937 | Method and structure for providing improved thermal conduction for silicon semiconductor devices Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps... | 05/30/2006 |
| 7046719 | Soft handoff between cellular systems employing different encoding rates A receiver (200) is provided receiving signals from differing base stations (BTSA and BTSB). The signal from BTSA is encoded using a first rate convolutional encoder while the signal transmitted from BTSB is encoded... | 05/16/2006 |
| 7030451 | Method and apparatus for performing nickel salicidation A method and apparatus for performing nickel salicidation is disclosed. The nickel salicide process typically includes: forming a processed substrate including partially fabricated integrated circuit components and a silicon substrate; incorporating nitrogen into th... | 04/18/2006 |
| 7018920 | Composite sacrificial material A composite sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The composite sacrificial material includes a polymeric or oligomeric matrix with filler material mixed therein. The filler material may be particu... | 03/28/2006 |
| 7018484 | Semiconductor-on-insulator silicon wafer and method of formation A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second silicon substrates. A first thin layer of silicon dioxide is formed on one substrate and a second thicker layer of silicon dioxide is forme... | 03/28/2006 |
| 7012011 | Wafer-level diamond spreader An embodiment of the present invention is a technique to heat spread at wafer level. A silicon wafer is thinned. A chemical vapor deposition diamond (CVDD) wafer processed. The CVDD wafer is bonded to the thinned silicon wafer to form a bonded wafer. Metallization i... | 03/14/2006 |
| 7009251 | SOI device with reduced junction capacitance An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also... | 03/07/2006 |
| 6995821 | Methods of reducing unbalanced DC voltage between two electrodes of reflective liquid crystal display by thin film passivation A structure (and method) for a reflective-type liquid crystal display includes a first-type electrode, a second-type electrode positioned opposite the first-type electrode and being of an opposite type than the first-type electrode and a liquid crystal material betw... | 02/07/2006 |
| 6979631 | Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion... | 12/27/2005 |
| 6969753 | Spin-on-glass anti-reflective coatings for photolithography Anti-reflective coating materials for deep ultraviolet photolithography include one or more organic light-absorbing compounds incorporated into spin-on-glass materials. Suitable absorbing compounds are strongly absorbing over wavelength ranges around wavelengths suc... | 11/29/2005 |
| 6967132 | Methods of forming semiconductor circuitry The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion... | 11/22/2005 |
| 6955988 | Method of forming a cavity and SOI in a semiconductor substrate A semiconductor substrate (1) comprising an SOI (2) formed therein. The semiconductor substrate (1) comprises first and second wafers (4,6) which are directly bonded together along a bond interface (9). Prior to bonding the wafers ... | 10/18/2005 |
