Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 6976155 | Method and apparatus for communicating between processing entities in a multi-processor A method and apparatus for synchronizing and communicating between processing entities, such as cores or threads, in a multiprocessor. Two registers are used as a “hardware mailbox” by two processing entities of a microprocessor. A first register is used to comm... | 12/13/2005 |
| 6973648 | Method and device to process multidimensional array objects A method for processing a multidimensional array object in which a multidimensional array is implemented by an array of array objects. The multidimensional array object comprises array objects which constitute the multidimensional array. Flags representing that it i... | 12/06/2005 |
| 6973131 | Decoding apparatus, decoding method, decoding processing program and computer-readable storage medium having decoding processing program codes stored therein A decoding processing method for decoding a plurality kinds of encoded streams comprises the steps of inputting a plurality kinds of encoded streams, determining priority among the inputted plurality kinds of encoded streams and decoding the plurality kinds of encod... | 12/06/2005 |
| 6971104 | Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction A method of performing a thread switching operation within a multithreaded processor includes detecting dispatch of a first predetermined quantity of instruction information of a first thread, from an instruction streaming buffer to an instruction pre-decoder within... | 11/29/2005 |
| 6971103 | Inter-thread communications using shared interrupt register A multithreaded processor includes an interrupt controller for processing a cross-thread interrupt directed from a requesting thread to a destination thread. The interrupt controller in an illustrative embodiment receives a request for delivery of the cross-thread i... | 11/29/2005 |
| 6968552 | Processor unit for executing event process in real time in response to occurrence of event A processor unit is incorporated in a vehicle as an engine control unit (ECU). In the ECU, in response to occurrence of an event, an activation request program requests a real time operating system to activate a task that includes an event process corresponding to t... | 11/22/2005 |
| 6968446 | Flags handling for system call instructions A processor is configured to support a programmable flags masking during processing of a system call instruction such as Syscall. The processor includes a register storing a mask, where an indication within the mask corresponds to each of a plurality of flags used b... | 11/22/2005 |
| 6965986 | Method and apparatus for implementing two-tiered thread state multithreading support with high clock rate A method and apparatus are provided for implementing two-tiered thread state multithreading support with a high clock rate. A first tier thread state storage stores a limited number of runnable thread register states. The limited number is less than a threshold valu... | 11/15/2005 |
| 6965984 | Data processing using multiple instruction sets A data processing system supports execution of both native instructions and Java bytecodes using a hardware executer for the Java bytecodes where possible and a software instruction interpreter for the Java bytecodes where these are not supported by the hardware. Th... | 11/15/2005 |
| 6965982 | Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread A method and processor architecture are provided that enables efficient pre-fetching of instructions for multithreaded program execution. The processor architecture comprises an instruction pre-fetch unit, which includes a pre-fetch request engine, a pre-fetch reque... | 11/15/2005 |
| 6965961 | Queue-based spin lock with timeout A queue-based spin lock with timeout allows a thread to obtain contention-free mutual exclusion in fair, FIFO order, or to abandon its attempt and time out. A thread may handshake with other threads to reclaim its queue node immediately (in the absence of preemption... | 11/15/2005 |
| 6964047 | Method and apparatus for a fast process monitor suitable for a high availability system An application initiates a parent process (102) to begin executing the application. The parent process (102) creates a child process (104) to execute the application. The parent monitors the death of the child process using inter-process communi... | 11/08/2005 |
| 6955264 | Method of detecting protrusion of inspection object from palette and method of fabricating semiconductor device In order to provide a method of detecting protrusion of an inspection object from a palette improved to be capable of making highly precise detection and reducing a socket breakage ratio, an inspection object is introduced into each of a plurality of pockets provide... | 10/18/2005 |
| 6957431 | System for incrementally computing the maximum cost extension allowable for subsequent execution of each task using fixed percentage of the associated cost The present invention provides a method, system, and computer program product for improving scheduling of tasks in systems that accumulate execution time. An upper bound is computed on the amount of additional time each schedulable task in the system may continue to... | 10/18/2005 |
| 6954933 | Method and apparatus for providing and integrating high-performance message queues in a user interface environment A method and apparatus is provided for providing and integrating high-performance message queues. “Contexts” are provided that allow independent worlds to be created and execute in parallel. A context is created with one or more threads. Each object is created w... | 10/11/2005 |
| 6952711 | Maximally negative signed fractional number multiplication A method and processor for multiplying two maximally negative fractional numbers to produce a 32-bit result are provided. Operands are fetched from a source location for operation of a multiplication operation. Result outputs corresponding to a maximally negative re... | 10/04/2005 |
| 6952214 | Method for context switching a graphics accelerator comprising multiple rendering pipelines A graphics system comprising a plurality of rendering pipelines and a scheduling network. Each rendering pipeline couples to the scheduling network, and includes a media processor, a rendering unit and a memory. A communication bus may couple the scheduling network ... | 10/04/2005 |
| 6952827 | User program and operating system interface in a multithreaded environment A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads execu... | 10/04/2005 |
| 6944699 | System and method for facilitating context-switching in a multi-context computer system A virtual machine monitor (VMM) is included in a computer system that has a protected host operating system (HOS). A virtual machine running at least one application via a virtual operating system is connected to the VMM. Both the HOS and the VMM have separate opera... | 09/13/2005 |
| 6941545 | Profiling of computer programs executing in virtual memory systems A computer. An instruction pipeline and memory access unit execute instructions in a logical address space of a memory of the computer. An address translation circuit translates address references generated by the program from the program's logical address space to ... | 09/06/2005 |
| 6937084 | Processor with dual-deadtime pulse width modulation generator A processor that has pulse width modulation generation circuitry that provides an improved ability to deal with the less than perfect switching characteristics of external switching devices that are connected to PWM hardware included in a processor. Complementary PW... | 08/30/2005 |
| 6938247 | Small memory footprint system and method for separating applications within a single virtual machine A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more “original” classes. Only one copy of each original class is maintained, regardless of how many applications utilize it. Static field... | 08/30/2005 |
| 6934952 | Method and apparatus for managing multiple instances of server code on a machine When multiple copies of a software program reside on a single machine and need to cooperate with each other to coordinate certain aspects of their execution, an election process is conducted to elect one of the copies as a master or supervisor copy, with the non-ele... | 08/23/2005 |
| 6934832 | Exception mechanism for a computer A computer has a multi-stage execution pipeline and an instruction decoder. The instruction decoder is designed (a) to decode instructions of a complex instruction set for execution by the pipeline, the instruction set being architecturally exposed for execution by ... | 08/23/2005 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing... | 08/23/2005 |
| 6931641 | Controller for multiple instruction thread processors A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back... | 08/16/2005 |
| 6928647 | Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor The present invention provides a method and apparatus for controlling a processing priority assigned alternately to a first thread and a second thread in a multithreaded processor to prevent deadlock and livelock problems between the first thread and the second thre... | 08/09/2005 |
| 6928645 | Software-based speculative pre-computation and multithreading Speculative pre-computation and multithreading (SP), allows a processor to use spare hardware contexts to spawn speculative threads to very effectively pre-fetch data well in advance of the main thread. The burden of spawning threads may fall on the main thread via ... | 08/09/2005 |
| 6922835 | Techniques for permitting access across a context barrier on a small footprint device using run time environment privileges A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same contex... | 07/26/2005 |
| 6920475 | Communication architecture for distributed computing environment A communication architecture for performing work in a distributed computing environment involves client processes on client nodes sending work requests to a director. The director examines the work requests to determine one or more resources required to perform the ... | 07/19/2005 |
| 6918114 | Method, apparatus, and program to keep a JVM running during the shutdown process of a Java based server executing daemon threads A single normal Java thread referred to as a “waiter” thread is used to prevent premature exit of the Java Virtual Machine during the shutdown process of the server application by waiting for any daemon threads in the JVM to complete execution. Using this mechan... | 07/12/2005 |
| 6915414 | Context switching pipelined microprocessor A single shared processing path is used as contexts are switched during processing. Each unique context is processed using a corresponding unique pipeline. If a pipeline that is executing under one context stalls, processing is switched in the shared processing path... | 07/05/2005 |
| 6912586 | Apparatus for journaling during software deployment and method therefor A method that, all-in-one, allows applications to distribute asynchronously large amounts of data from a source node to multiple destination nodes, to process that data on each single node and to collect the results of that processing on one or more report-to nodes.... | 06/28/2005 |
| 6910213 | Program control apparatus and method and apparatus for memory allocation ensuring execution of a process exclusively and ensuring real time operation, without locking computer system A program control apparatus ensuring real time response by ensuring execution of a process exclusively without locking the system includes a unit responsive to an application program interface call from a thread which interface requesting start of detection of prese... | 06/21/2005 |
| 6907515 | Configuration control within data processing systems A data processing system is provided with a first mechanism for executing instructions of a first instruction set and a second mechanism for executing instructions of a second instruction set. The second mechanism requires configuration data 310, 312, 314, 316 | 06/14/2005 |
| 6907608 | Techniques for permitting access across a context barrier in a small footprint device using global data structures A small footprint device can securely run multiple programs from unrelated vendors by the inclusion of a context barrier isolating the execution of the programs. The context barrier performs security checks to see that principal and object are within the same namesp... | 06/14/2005 |
| 6904511 | Method and apparatus for register file port reduction in a multithreaded processor Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select ... | 06/07/2005 |
| 6904594 | Method and system for apportioning changes in metric variables in an symmetric multiprocessor (SMP) environment A method and system for monitoring performance of a program using global metric variables to provide the support in an symmetric multiprocessor (SMP) system. A Java virtual machine (Jvm) either calls the profiler whenever bytes are allocated or provides an interface... | 06/07/2005 |
| 6895583 | Task control block for a computing environment A task control block is implemented to provide more efficient user task access to task-specific variables and context information. The task control block uses multiple portions located in both protected system space and unprotected “user” space. Task-specific va... | 05/17/2005 |
| 6886165 | Method for the direct call of a function by a software module by means of a processor with a memory-management unit (MMU) A method for the direct call of a target function by a start function by means of a processor with a memory management unit (MMU) in a computer operated by an operating system. In today's multitasking operating systems, the call of a function of a first task by a se... | 04/26/2005 |
