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| Number | Title | Issue Date |
| 8191057 | Systems, methods, and computer products for compiler support for aggressive safe load speculation Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a computer system, the method including building a control flow graph, ide... | 05/29/2012 |
| 8191056 | Sparse vectorization without hardware gather/scatter A target operation in a normalized target loop, susceptible of vectorization and which may, after compilation into a vectorized form, seek to operate on data in nonconsecutive physical memory, is identified in source code. Hardware instructions are inserted into exe... | 05/29/2012 |
| 8141068 | Compiler with flexible scheduling A computer program consisting of a compiler for compiling source code programs into executable code. The compiler is suited to achieving high efficiency on a processor that can process many instructions at once but the instructions have dependency constraints and th... | 03/20/2012 |
| 8091079 | Implementing shadow versioning to improve data dependence analysis for instruction scheduling A method for implementing shadow versioning to improve data dependence analysis for instruction scheduling in compiling code, and to identify loops within the code to be compiled, for each loop initializing a dependence a matrix, for each loop shadow identifying sym... | 01/03/2012 |
| 7979853 | Compiler device, method, program and recording medium Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a ... | 07/12/2011 |
| 7962907 | Scheduling technique for software pipelining An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple s... | 06/14/2011 |
| 7930688 | Scheduling technique for software pipelining An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple s... | 04/19/2011 |
| 7895587 | Single-chip multiprocessor with clock cycle-precise program scheduling of parallel execution A single-chip multiprocessor system and operation method of this system based on a static macro-scheduling of parallel streams for multiprocessor parallel execution. The single-chip multiprocessor system has buses for direct exchange between the processor register f... | 02/22/2011 |
| 7865887 | Context based event handling and execution with prioritization and interrupt management Embodiments of the present invention provide improved event handling between systems. In one embodiment, the present invention includes software event handling method comprising receiving a first event from a first source system in a plurality of source systems, the... | 01/04/2011 |
| 7814469 | Speculative multi-threading for instruction prefetch and/or trace pre-build The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main t... | 10/12/2010 |
| 7797692 | Estimating a dominant resource used by a computer program A system that estimates a dominant computational resource which is used by a computer program. During operation, for each basic block in the computer program, the system determines a nesting level for the basic block. Next, the system selects basic blocks with nesti... | 09/14/2010 |
| 7765536 | System and method for the distribution of a program among cooperating processors A Veil program analyzes the source code and data of a target program and determines how best to distribute the target program and data among the processors of a multi-processor computing system. The Veil program analyzes source code loops, data sizes and types to pr... | 07/27/2010 |
| 7681188 | Locked prefetch scheduling in general cyclic regions One embodiment of the present invention provides a system that facilitates locked prefetch scheduling in general cyclic regions of a computer program. The system operates by first receiving a source code for the computer program and compiling the source code into in... | 03/16/2010 |
| 7673296 | Method and system for optional code scheduling A method of scheduling optional instructions in a compiler targets a processor. The scheduling includes indicating a limit on the additional processor computations that are available for executing an optional code, generating one or more required instructions corres... | 03/02/2010 |
| 7657883 | Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor A dispatch scheduler in a multithreading microprocessor is disclosed. Each of N concurrently executing threads has one of P priorities. P N-bit round-robin vectors are generated, each being a 1-bit left-rotated and subsequently sign-extended version of an N-bit 1-ho... | 02/02/2010 |
| 7631305 | Methods and products for processing loop nests Methods and products for processing a software kernel of instructions are disclosed. The software kernel has stages representing a loop nest. The software kernel is processed by partitioning iterations of an outermost loop into groups with each group representing it... | 12/08/2009 |
| 7617496 | Macroscalar processor architecture A macroscalar processor architecture is described herein. In one embodiment, a processor receives instructions of a program loop having a vector block and a sequence block intended to be executed after the vector block, where the processor includes multiple slices a... | 11/10/2009 |
| 7617495 | Resource-aware scheduling for compilers Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when determining priority for scheduling of instructions. Other embodiments ... | 11/10/2009 |
| 7571435 | Method and structure for producing high performance linear algebra routines using preloading of floating point registers A method (and structure) for executing linear algebra subroutines, includes, for an execution code controlling operation of a floating point unit (FPU) performing the linear algebra subroutine execution, unrolling instructions to preload data into a floating point r... | 08/04/2009 |
| 7523449 | System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implemen... | 04/21/2009 |
| 7509634 | SIMD instruction sequence generating program, SIMD instruction sequence generating method and apparatus A translator receives a source code that is described using a process designation (such as a line-by-line process designation, a line data extraction designation, and a broadcast designation) to be performed on line data of an image on a line by line basis, parses a... | 03/24/2009 |
| 7478379 | Method for minimizing spill in code scheduled by a list scheduler A technique of ordering machine instructions to reduce spill code. For each machine instruction that is ready for scheduling, an amount is determined by which the size of a committed set of machine instructions would increase upon the scheduling of the machine instr... | 01/13/2009 |
| 7448031 | Methods and apparatus to compile a software program to manage parallel μcaches Methods and apparatus to compile a software program to manage parallel μ caches are disclosed. In an example method, a compiler attempts to schedule a software program such that load instructions in a first set of load instructions has a first predetermine latency ... | 11/04/2008 |
| 7444628 | Extension of swing modulo scheduling to evenly distribute uniform strongly connected components A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency. Determine whether the series of instructions is a uniform series o... | 10/28/2008 |
| 7441110 | Prefetching using future branch path information derived from branch prediction A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while... | 10/21/2008 |
| 7434211 | Transient shared computer resource and settings change bubble for computer programs Described is a mechanism that preserves the state of computer system shared resources and/or settings, and ensures that changes thereto are reverted when an application exits. A shared resource change bubble logically surrounds application code that causes system re... | 10/07/2008 |
| 7415700 | Runtime quality verification of execution units One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of ... | 08/19/2008 |
| 7401329 | Compiling computer programs to exploit parallelism without exceeding available processing resources A compilation technique for computer programs forms a data flow graph of vertices which are analysed to form clusters C for parallel execution where those clusters are added to up to the point at which arbitrary selection between further vertices C, D to be added mu... | 07/15/2008 |
| 7395531 | Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler... | 07/01/2008 |
| 7395532 | Process for running programs on processors and corresponding processor system Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of ins... | 07/01/2008 |
| 7389385 | Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system ... | 06/17/2008 |
| 7386844 | Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can ex... | 06/10/2008 |
| 7383544 | Compiler device, method, program and recording medium Compiler device optimizes a program by changing an order of executing instructions. The device includes: a replaceability determination unit which determines whether a first instruction included in a first instruction sequence and a second instruction included in a ... | 06/03/2008 |
| 7373377 | Interactive virtual thematic environment The present invention is directed to a method of integrating information, including real-time information, into a virtual thematic environment using a computer system, including accessing the stored information from a database or downloading the real-time informatio... | 05/13/2008 |
| 7370321 | Systems and methods to read, optimize, and verify byte codes for a multiplatform jit A byte code reader provides verification while optimizing and creating an internal SSA form to allow efficient machine code generation. Many functions are combined in one component honoring the difficult time constraints of just-in-time translation. This reader is e... | 05/06/2008 |
| 7360209 | Object process graph application controller-viewer A computer software system is provided, namely, An Object Process Graph Application Controller-Viewer (OPGACV) system. The OPGACV controls a running Object Process Graph (OPG) application by inducing a Dynamic Graph Interpreter (DGI) to transition applications from ... | 04/15/2008 |
| 7360015 | Preventing storage of streaming accesses in a cache In one embodiment of the present invention, a method may include determining whether requested information is part of a streaming access, and directly writing the requested information from a storage device to a memory if the requested information is part of the str... | 04/15/2008 |
| 7353503 | Efficient dead code elimination Disclosed is a method for eliminating dead code from a computer program using an operands graph generated from a flow graph of a computer program. In one embodiment of the present invention, the operands graph is traversed for any unused operands. Upon detection of ... | 04/01/2008 |
| 7350061 | Assigning free register to unmaterialized predicate in inverse predicate expression obtained for branch reversal in predicated execution system Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The predicate expression is employed to enable a transformation to be ma... | 03/25/2008 |
| 7337439 | Method for increasing the speed of speculative execution A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been sele... | 02/26/2008 |
