Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8191055 | Method and software for optimising the positioning of software functions in a memory The present invention is related to a method and a software program for optimizing the positioning of software functions in a memory of a computing device. The present invention hereby comprises the steps of identifying each of a number of software functions and the... | 05/29/2012 |
| 8181170 | Unwind information for optimized programs Analyzing a first binary version of a program and unwind information associated with the first binary version of the program, performing optimization on the first binary version of the program to produce a second binary version of the program based at least in part ... | 05/15/2012 |
| 8156484 | LDAP server performance object creation and use thereof A system in which a plurality of performance objects are stored in computer memory, where each performance objects contains at least one input template and a corresponding optimized code path program product. A template matcher intercepts an input set destined to a ... | 04/10/2012 |
| 8141063 | Static analysis of reachable methods and fields in object-oriented applications using object instantiation Exemplary embodiments of the present invention comprise an algorithm described herein that utilizes a technique to shrink a set of potentially reachable elements to a close approximation of the actually reachable elements within a software application by closely app... | 03/20/2012 |
| 8141064 | Method and system for program transformation using flow-sensitive type constraint analysis A method for analyzing a program is provided. The method includes, determining an object type that may exist at an execution point of the program, wherein this enables determination of possible virtual functions that may be called; creating a call graph at a main en... | 03/20/2012 |
| 8117605 | Method and apparatus for improving transactional memory interactions by tracking object visibility In a multi-threaded computer system that uses transactional memory, object fields accessed by only one thread are accessed by regular non-transactional read and write operations. When an object may be visible to more than one thread, access by non-transactional code... | 02/14/2012 |
| 8015556 | Efficient method of data reshaping for multidimensional dynamic array objects in the presence of multiple object instantiations A method of data reshaping for multidimensional dynamic array objects in the presence of multiple object instantiations. The method includes collecting all alias information using interprocedural point escape analysis, and collecting all shape information using inte... | 09/06/2011 |
| 8006239 | Program analysis using symbolic ranges A computer implemented method for generating a representation of relationships between variables in a program employing Symbolic Range Constraints (SRCs) wherein the SRCs are of the form φ:^i=1nli≦xi≦ui whe... | 08/23/2011 |
| 7979852 | System for automatically generating optimized codes The inventive system for automatically generating optimizes codes (19) which are operational on a predefined hardware platform (90) comprises at least one processor which is (91) based on code sources (17) provided by users and comprises ... | 07/12/2011 |
| 7882500 | Method and a system for composing an optimally-grained set of service functions Disclosed is a computer program product for managing granularity of a computing infrastructure, wherein the program, when executed on a computer, causes the computer to: identify at least one set of service functions suited to characterization by one or more sets of... | 02/01/2011 |
| 7873953 | High-level language code sequence optimization for implementing programmable chip designs Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the... | 01/18/2011 |
| 7873952 | Code transformation to optimize fragments that implement constant loading A code, which may be a post-link binary or a pre-link object file, can be transformed to optimize code fragments that implement loading a constant from memory. A constant loading code fragment includes address computing operations that compute (or copy) an address r... | 01/18/2011 |
| 7788656 | System for reducing the number of programs necessary to render an image Disclosed is as system for reducing memory and computational requirements of graphics operations. The system provides techniques for combining otherwise individual operations to apply filters to images. The combined filter emerging from the combination spares the pr... | 08/31/2010 |
| 7779399 | System and method for securing web application code and verifying correctness of software Methods, software tools and systems for analyzing software applications, e.g., Web applications, are described. A software application to be analyzed is transformed into an abstract representation which preserves its information flow properties. The abstract interpr... | 08/17/2010 |
| 7765533 | Automatic task distribution in scalable processors A processing method and apparatus for processing an information is based on a sequence of instructions, where a repeated sub-sequence is detected in the sequence of instructions and an allocation between a processing resource and the repeated sub-sequence is determi... | 07/27/2010 |
| 7765534 | Compiler with cache utilization optimizations A compiling program with cache utilization optimizations employs an inter-procedural global analysis of the data access patterns of compile units to be processed. The global analysis determines sufficient information to allow intelligent application of optimization ... | 07/27/2010 |
| 7721275 | Data-flow based post pass optimization in dynamic compilers A system and method to perform post pass optimizations in a dynamic compiling environment. A dynamic compiler emits machine code. Responsive to the emission of the machine code a post pass processor creates an abstract representation of the code from the dynamic com... | 05/18/2010 |
| 7685585 | Creating an explicit flow control in an implicit flow programming environment Creating explicit control flow in an implicit control flow development environment. A set of explicit functions is defined in a library associated with the implicit control flow development environment. Each of the explicit functions in the set is associated with a ... | 03/23/2010 |
| 7685586 | Global escape analysis using instantiated type analysis Global escape analysis using instantiated type analysis (ITA) is applied to a method of an object-oriented application to analyze control flow beginning with an invocation of the method. The instantiated type analysis methodology (inter-procedural control flow analy... | 03/23/2010 |
| 7624388 | Caching run-time variables in optimized code In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and definin... | 11/24/2009 |
| 7584462 | System for optimizing application start-up A method for decreasing a computer application's start-up time. In one aspect, the method comprises: creating a serialized representation of application objects in a runtime environment; building an object code file using the serialized representation; and providing... | 09/01/2009 |
| 7571434 | Method and apparatus for transparent invocation of a characteristics extractor for pattern-based system design analysis A method for analyzing a target system that includes obtaining a plurality of characteristics from the target system using a characteristics extractor and at least one selected from the group consisting of a software build project associated with the target system a... | 08/04/2009 |
| 7555747 | Prediction mechanism for subroutine returns in binary translation sub-systems of computers A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host system, which executes the OL instructions. In order to determine the retur... | 06/30/2009 |
| 7503039 | Preprocessor to improve the performance of message-passing-based parallel programs on virtualized multi-core processors Provided is a complier which optimizes parallel processing. The complier records the number of execution cores, which is the number of processor cores that execute a target program. First, the compiler detects a dominant path, which is a candidate of an execution pa... | 03/10/2009 |
| 7500232 | Methods for enhancing flow analysis Methods and structures are described that enhance flow analysis for programs. Whereas previous methods are complicated by the presence of function pointers, the present methods present a framework that abstracts function pointers as if they were any other program ex... | 03/03/2009 |
| 7493609 | Method and apparatus for automatic second-order predictive commoning A method and apparatus for automatic second-order predictive commoning is provided by the present invention. During an analysis phase, the intermediate representation of a program code is analyzed to identify opportunities for second-order predictive commoning optim... | 02/17/2009 |
| 7467377 | Methods and apparatus for compiler managed first cache bypassing Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instr... | 12/16/2008 |
| 7451438 | Method, system and product for identifying and executing locked read regions and locked write regions in programming languages that offer synchronization without explicit means to distinguish between such regions A technique for identifying and executing synchronized read regions and synchronized write regions is provided. The technique processes program code with a software tool to convert the code to an internal representation for the software tool and constructs a control... | 11/11/2008 |
| 7444628 | Extension of swing modulo scheduling to evenly distribute uniform strongly connected components A method, apparatus, and computer instructions for scheduling instructions for execution. Identify a series of instructions in a loop, wherein the series of instructions has a cyclic data dependency. Determine whether the series of instructions is a uniform series o... | 10/28/2008 |
| 7444626 | Apparatus and method for linear dead store elimination An apparatus and method for removing stores to local variables that are not aliased by other variables or to variables which have already been removed by previous optimizations prior to performing dead store elimination optimization are provided. With the method and... | 10/28/2008 |
| 7434002 | Utilizing cache information to manage memory access and cache utilization In a method of optimizing utilization of a shared cache, a set of locations in the cache is probed. The probing takes place while an observed process is running, descheduled, or interrupted. It is determined which portions of the cache are utilized by the observed p... | 10/07/2008 |
| 7430733 | Method for validation of binary code transformations A method of validating binary code transformation in one aspect includes analyzing original program and transform program. Control flow graphs are generated for both programs. The two graphs are traversed to create respective linear invariant representations. The li... | 09/30/2008 |
| RE40498 | Variable address length compiler and processor improved in address management The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the conver... | 09/09/2008 |
| 7412684 | Loop manipulation in a behavioral synthesis tool Methods and apparatus for analyzing and processing loops within an integrated circuit design are described. According to one embodiment, the processing comprises unrolling loops. In another embodiment, the processing comprises pipelining loops. In yet another embodi... | 08/12/2008 |
| 7409675 | Code rewriting Systems and methods provide for the rewriting and transformation of a code unit through an extensible, composable, set of code rewriters that can be implemented at various phases throughout the development, deployment, and execution of the code unit. The described s... | 08/05/2008 |
| 7401329 | Compiling computer programs to exploit parallelism without exceeding available processing resources A compilation technique for computer programs forms a data flow graph of vertices which are analysed to form clusters C for parallel execution where those clusters are added to up to the point at which arbitrary selection between further vertices C, D to be added mu... | 07/15/2008 |
| 7395529 | Conflict detection and correction in a program build environment A method is described for executing program builds comprising: scheduling jobs for a program build based on dependencies between files used in the jobs; executing the jobs according to the schedule; collecting file usage information from each of the jobs, the file u... | 07/01/2008 |
| 7392516 | Method and system for configuring a dependency graph for dynamic by-pass instruction scheduling There is disclosed a method and system for configuring a data dependency graph (DDG) to handle instruction scheduling in computer architectures permitting dynamic by-pass execution, and for performing dynamic by-pass scheduling utilizing such a configured DDG. In ac... | 06/24/2008 |
| 7392513 | Methods and apparatus for merging critical sections Methods and apparatus for merging critical sections are disclosed. An example disclosed system estimates the cost of merging a first critical section and a second critical section using a dataflow analysis on the first and second critical sections. In the example sy... | 06/24/2008 |
| 7389501 | System and method for register allocation using SSA construction The construction of Static Single Assignment form (SSA) is used as a dynamic conflict graph so that while constructing SSA in linear time, the program being analyzed is simultaneously register allocated. When allocating a register for the symbol, the conflict set is... | 06/17/2008 |
