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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 6539541 | Method of constructing and unrolling speculatively counted loops A method of constructing and unrolling speculatively counted loops. The method of the present invention first locates a memory load instruction within the loop body of a loop. An advance load instruction is inserted into the preheader of the loop. The mem... | 03/25/2003 |
| 6484314 | Exception handling method and system The present invention provides a method and a system for generating an exception handling instruction and for avoiding the execution of unnecessary instructions. More particularly, an internal opcode in a compiler is read and one internal opcode is obtain... | 11/19/2002 |
| 6477641 | Method for translating between source and target code with heterogenous register sets An interactive translation system (10) includes a front end (40), a back end (42), and a user interface (16). The front end (40) is operable to identify source elements (86) in a source file (24). The back end (42) is operable to generate a translation fi... | 11/05/2002 |
| 6374403 | Programmatic method for reducing cost of control in parallel processes A parallel compiler exploits temporal recursion to reduce the cost of control code generated in transforming a sequential nested loop program into a set of parallel processes mapped to an array of processors. A parallel compiler process transforms a neste... | 04/16/2002 |
| 6292939 | Method of reducing unnecessary barrier instructions Unnecessary barrier instructions are dynamically reduced in a parallel processing object program, program module or object code section to be parallel processed in a multiprocessor system by a compiler that generates the parallel processing object program... | 09/18/2001 |
| 6286135 | Cost-sensitive SSA-based strength reduction algorithm for a machine with predication support and segmented addresses A compiler optimization algorithm that deals with aggressive strength reduction of integer machine instructions found in loops. The algorithm permits the strength reduction of such machine instructions whose execution may be guarded by predicate values. I... | 09/04/2001 |
| 6282706 | Cache optimization for programming loops A cache memory architecture 50, which may be, for example, a set associative cache memory, has a cache controller (52) with an internal register for storing the address of the active line currently latched in the output buffer of the high speed cache data... | 08/28/2001 |
| 6282704 | Method for analyzing array summary for loop including loop exit statement A method for analyzing an array summary to improve the accuracy of an array summary analysis of a loop containing a loop exit statement, thereby to improve applicability of array privatization. If a loop exit statement and a statement that sets the value ... | 08/28/2001 |
| 6282702 | Method and apparatus of translating and executing native code in a virtual machine environment A method and apparatus of translating and executing native code in a virtual machine environment. Debugging of a virtual machine implementation is made easier through binary translation of native code, which permits greater platform independence and great... | 08/28/2001 |
| 6279152 | Apparatus and method for high-speed memory access When a processing unit of a vector computer detects an optimization directive line for optimizing a list accessing method during the compilation, an access method is automatically changed according to an instruction of the directive line. For example, dat... | 08/21/2001 |
| 6272676 | Method and apparatus for finding loop-- lever parallelism in a pointer based application A method and apparatus for finding loop_level parallelism in a sequence of instructions. In one embodiment, the method includes the steps of determining if a variable which identifies a memory address of a data structure is an induction variable; and dete... | 08/07/2001 |
| 6269440 | Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously An apparatus and method that speeds the processing of data vectors in a digital processor is disclosed. In accordance with the present invention, a vector zero overhead loop with parallel issue processes multiple data elements at the same time, and yet is... | 07/31/2001 |
| 6253373 | Tracking loop entry and exit points in a compiler The inventive system and method separates the tracking of the loop entry and exit points and loop optimization information, from the generation of the instrumentation code at the loop entry and exit points. Thus, the different phases in the compiler can p... | 06/26/2001 |
| 6253371 | Method for supporting parallelization of source program In order to generate a source program or an object code which can be executed in parallel efficiency by detecting an independent operation of a large grain size from a program which can not be analyzed by the compiler, a parallelization supporting tool in... | 06/26/2001 |
| 6088525 | Loop profiling by instrumentation The inventive system and method prepares a loop within a section of program code for profiling by placing instrumentation slots into the section at particular points. Entry slots are inserted just prior to the entry point of the loop. If there is a target... | 07/11/2000 |
| 6074433 | Optimization control apparatus and optimization control method for array descriptions In order to generate optimum codes for array descriptions having a new language specification, an optimization control apparatus or method for array description executes a function of determining a scope of executing optimization for the array description... | 06/13/2000 |
| 6038396 | Compiling apparatus and method for a VLIW system computer and a recording medium for storing compile execution programs A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each slot of the VLIW instruction, is divided corresponding... | 03/14/2000 |
| 6016399 | Software pipelining a hyperblock loop An iterative software pipelining method promotes instructions of a program loop to previous loop iterations and then reschedules the instructions until either 1) the resultant schedule is optimal (i.e., the initiation interval is equal to the minimal init... | 01/18/2000 |
| 5850551 | Compiler and processor for processing loops at high speed A compiler comprises a loop detecting unit for extracting information of loops, and a high-speed loop applying unit generating a first loop exclusive instruction, placing the instruction immediately before the entry of a loop, generating second loop exclu... | 12/15/1998 |
| 5835776 | Method and apparatus for instruction scheduling in an optimizing compiler for minimizing overhead instructions Apparatus and methods are disclosed for scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modern microprocessors have the ability to issue multiple instructions in one clock cycle and/or possess multi... | 11/10/1998 |
| 5809308 | Method and apparatus for efficient determination of an RMII vector for modulo scheduled loops in an optimizing compiler Apparatus and methods are disclosed for determining a recurrence minimum iteration interval (rmii) vector for use in modulo scheduling target program instructions during the code optimization pass of an optimizing compiler. Most modem microprocessors have... | 09/15/1998 |
| 5802375 | Outer loop vectorization A system and method for vectorizing a non-innermost loop of a nested loop. Iterative loops of a nested loop are analyzed to determine if they can be vectorized (vector legality). If more than one iterative loop can be vectorized, a selection criteria is a... | 09/01/1998 |
| 5797013 | Intelligent loop unrolling A compiler facilitates efficient unrolling of loops and enables the elimination of extra branches from the loops, including the elimination of conditional branches from unrolled loops with early exits. Unrolling also enhances other optimizations, such as ... | 08/18/1998 |
| 5790854 | Efficient stack utilization for compiling and executing nested if-else constructs in a vector data processing system A computer-implemented method is provided for compiling software code that performs nested conditional constructs in vector data processors (10). A vector bit stack (128) to record which processing elements (16) were activated and which processing element... | 08/04/1998 |
| 5781777 | Optimization method for computation partitioning oriented to a distributed memory When a loop contains a plurality of statements, a compiled program is generated without performing loop distribution, the resultant loop having no runtime resolution statement. A parallelizing compiler comprises a syntax analysis section, a data distribut... | 07/14/1998 |
| 5774727 | Parallel processing system for virtual processor implementation of machine-language instructions A language construct that allows a software programmer to use an intermediate or high-level language command to explicitly group operations or fuse loops in a group of statements operating on parallel arrays is disclosed. The command instructs a compiler,... | 06/30/1998 |
| 5764993 | Data updating method using overlap area and program converting device for converting update program in distributed-memory parallel processor In a parallel processor, a local area and an overlap area are assigned to the memory of each processing element (PE), and each PE makes calculations to update the data in both areas at the runtime. If the data in the overlap area is updated in processes c... | 06/09/1998 |
| 5551039 | Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-stan... | 08/27/1996 |
| 5537620 | Redundant load elimination on optimizing compilers A method for eliminating redundant loads in an optimizing compiler is provided. When a LOAD and memory operation occur in an iterative loop structure having an induction variable, the method determines if redundant load elimination optimization may be per... | 07/16/1996 |
| 5522074 | Vectorization system for vectorizing loop containing condition induction variables A vectorization system is constituted with a conditional induction variable detector portion, a conditional induction variable reference state analyzing portion and a conditional induction variable iteration generator portion. The conditional induction va... | 05/28/1996 |
| 5485619 | Array variable transformation system employing subscript table mapping to scalar loop indices A subscript table mapping system for optimizing the compilation of certain Fortran 90 array construction and array manipulation transformation functions. The subscript table data object of this invention is used to perform the three compiler optimizations... | 01/16/1996 |
| 5481723 | System and method for controlling execution of nested loops in parallel in a computer including multiple processors, and compiler for generating code therefore A system and method for controlling execution of nested loops in parallel in a computer including multiple processors, and a compiler for generating code therefor. The code enables the computer to operate in the following manner. Each processor processes ... | 01/02/1996 |
| 5317734 | Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies A method of synchronizing the parallel processors of a multiple instruction stream multiprocessor employs a limited number of register channels, which may be re-used, for enforcing cross-stream data or event dependencies by passing data or event notificat... | 05/31/1994 |
| 5247696 | Method for compiling loops having recursive equations by detecting and correcting recurring data points before storing the result to memory A vector update method for vectorizing loops containing recursive equations within a supercomputer. Program code containing a loop is transformed into a nested loop in which the interior loop performs an integer number of iterations of the original loop e... | 09/21/1993 |
| 5230053 | Processor scheduling method for iterative loops A compiling method is described whereby a source program written in a conventional high-language for execution by a serial architecture computer can be automatically converted to an object program for parallel execution by a multi-processor computer, with... | 07/20/1993 |
| 5193192 | Vectorized LR parsing of computer programs A parser for parsing computer programs in a compiler has parsing tables arranged as linear vectors. In a reduction portion of the parser, a production table and a lookahead set table have paired entries at identical address offsets such that a one-to-one ... | 03/09/1993 |
| 5151991 | Parallelization compile method and system In order to make parallel processing of a serial execution type user program automatically and at a high speed without re-coding, an object code is parallelized by detection of the possibility of parallel execution in an iteration unit of a loop, detectio... | 09/29/1992 |
| 5146594 | Method of producing object program based on interprocedural dataflow analysis of a source program A method of producing an object program from an inputted source program with a compiler using a computer, includes the steps of: performing an interprocedural dataflow analysis of a variable associated with a procedure such as a subroutine, function, and ... | 09/08/1992 |
| 5088034 | Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors A compiler for generating from a serially processed type source program described in a high level language the object codes to be executed in parallel by a parallel processor system which is composed of a plurality of processors marked with respective ide... | 02/11/1992 |
| 4663704 | Universal process control device and method for developing a process control loop program A distributed processing unit (DPU) or drop which performs process control and data acquisition functions in a distributed processing control system having a data highway linking a plurality of such units. A DPU functional processor accesses the local pro... | 05/05/1987 |
