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Mouse device with a built-in printer
A mouse device for use as an input device of a computer is provided that includes a housing in which recording paper is loadable, and a printer unit provided within the housing for printing on the recording paper print information received from the computer.
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| Number | Title | Issue Date |
| 7890906 | Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cel... | 02/15/2011 |
| 7877718 | Analog IC placement using symmetry-islands A placement tool searches for an optimal placement for a plurality of device modules within an integrated circuit (IC) including symmetry groups formed by device modules that are to be symmetrically placed. The tool employs a hierarchical B*-tree (HB*-tree) represen... | 01/25/2011 |
| 7877719 | Fast dual-buffer insertion and buffered tree construction for power minimization Integrated circuit apparatus and methods are described for inserting multi-Vdd buffers within an interconnection tree during routing toward minimization of power under a delay constraint. Insertion of level converters is not necessary within the routing t... | 01/25/2011 |
| 7873928 | Hierarchical analog IC placement subject to symmetry, matching and proximity constraints A placement tool generates an optimal placement for a plurality of device modules within an analog integrated circuit (IC) subject to device matching, symmetry, and proximity constraints by first defining a multiple-level hierarchy of constraint groups, wherein each... | 01/18/2011 |
| 7861202 | Cell arrangement method for designing semiconductor integrated circuit Logic circuit information in which flip-flops of a semiconductor integrated circuit subjected to designing and a logic circuit between flip-flops are defined is input. The logic circuit information is analyzed to detect a logic circuit sandwiched by two flip-flops. ... | 12/28/2010 |
| 7840927 | Mutable cells for use in integrated circuits An integrated circuit implementation methodology uses mutable cells, e.g. cells that are capable of being personalized for use as one of a plurality of resource types. For example, a mutable cell is designed to have a component layout and a set of lower-layer intern... | 11/23/2010 |
| 7793246 | Method for forming matching table of inner pads and outer pads and method for matching inner pads with outer pads using the same A method for forming a matching table of inner pads and outer pads includes the steps of: obtaining a pitch Pi and a space Si between two neighboring inner pads; computing Wim=m×Pi−Si; obtaining a pitch P | 09/07/2010 |
| 7761830 | Method and system for providing placement based configurations in integrated circuits A method for providing placement based configurations in integrated circuits and integrated circuits having configurable data files for logic blocks based on the location of the blocks therein are disclosed. Location information for at least one logic block in an in... | 07/20/2010 |
| 7761829 | Graphical specification of relative placement of circuit cells for repetitive circuit structures A graphical specification entry interface allows a circuit designer to define relative placement of repeating circuit component cells. The repetitive placement specifications are used to generate a repetitively structured circuit cell which may be subsequently insta... | 07/20/2010 |
| 7757194 | Method and system for generating implementation files from a high level specification A method and system for generating implementation files from a high level specification are described. In one example, a method for creating a package file for an integrated circuit is described. First, a grid is formed having a plurality of blocks. A height and a w... | 07/13/2010 |
| 7739644 | Methods, systems, and computer program products for grid-morphing techniques in placement, floorplanning, and legalization Disclosed are methods, systems, and computer program products for performing grid morphing technique for computing a spreading of objects over an area such that the final locations of the objects are distributed over the area and such that the final locations of the... | 06/15/2010 |
| 7716617 | Semiconductor device, method for making pattern layout, method for making mask pattern, method for making layout, method for manufacturing photo mask, photo mask, and method for manufacturing semiconductor device A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection a... | 05/11/2010 |
| 7703062 | Semiconductor integrated circuit and method of designing layout of the same A semiconductor integrated circuit includes: a first boundary cell having a first power source wiring, a second power source wiring and a first pseudo power source wiring; a first circuit cell having a third power source wiring connected with the first power source ... | 04/20/2010 |
| 7685550 | Method for designing integrated circuits comprising replacement logic gates In a method for designing integrated circuits comprising replacement logic components, a plurality of logic cells and a plurality of filler cells which fill interspaces between the logic cells are positioned on a chip area. In this case, some or all of the filler ce... | 03/23/2010 |
| 7681166 | Method and apparatus for performing dummy-fill by using a set of dummy-fill cells An embodiment performs dummy fill in a design layout to achieve a target density that is within a narrow range of target densities. During operation, the system can receive a design layout that includes a region whose density is not within a desired range of target ... | 03/16/2010 |
| 7681165 | Apparatus and methods for congestion estimation and optimization for computer-aided design software A method of performing placement of resources in a computer-aided design (CAD) tool includes performing a first congestion analysis, proposing a placement move, and evaluating the placement move. The method further includes incrementally updating information used fo... | 03/16/2010 |
| 7669160 | Methods and systems for placement Simultaneous Dynamical Integration modeling techniques are applied to placement of elements of integrated circuits as described by netlists specifying interconnection of devices. Solutions to a system of coupled ordinary differential equations in accordance with New... | 02/23/2010 |
| 7657858 | Automated electrostatic discharge structure placement and routing in an integrated circuit A processor-implemented means of designing a power pad layout includes determining a location of at least one ESD structure so as to minimize a placement cost and determining a location of at least one connection between the at least one ESD structure and at least o... | 02/02/2010 |
| 7640522 | Method and system for placing layout objects in a standard-cell layout A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the l... | 12/29/2009 |
| 7620922 | Method and system for optimized circuit autorouting An approach is provided for selectively optimizing a circuit design, including generating a circuit routing solution according to a plurality of constraints for parametric resources of the circuit design, with the constraints being defined respectively by a pluralit... | 11/17/2009 |
| 7594212 | Automatic pin placement for integrated circuits to aid circuit board design A computer-implemented method of placing input/output (I/O) pins of a circuit design for an integrated circuit (IC) can include selecting a bus from a plurality of buses, where the selected bus includes a plurality of I/O pins and is part of an interface, and, for e... | 09/22/2009 |
| 7590960 | Placing partitioned circuit designs within iterative implementation flows A method of placing circuit elements of a partitioned circuit design on a target programmable logic device (PLD) can include mapping circuit elements of the circuit design to corresponding partitions of the circuit design, selecting a circuit element of the circuit ... | 09/15/2009 |
| 7584445 | Sequence-pair creating apparatus and sequence-pair creating method A sequence-pair creating apparatus includes a block placement storing unit that stores information of size of a block bi in a block set B and information of block placement, creates a sequence-pair (P, M), serving as a pair of a sequence P and a sequence ... | 09/01/2009 |
| 7568177 | System and method for power gating of an integrated circuit Apparatus and method aspects for power gating of an integrated circuit (IC) include providing at least one I/O power pad of an IC with a switch arrangement. The at least one I/O power pad is utilized to control a power signal transfer to at least a portion of the IC... | 07/28/2009 |
| 7562326 | Method of generating a standard cell layout and transferring the standard cell layout to a substrate A method of generating a standard cell layout includes analyzing a circuit of a standard cell layout and obtaining an analysis result, selecting a plurality of leaf cell layout according to the analysis result, and piecing together the leaf cell layouts to generate ... | 07/14/2009 |
| 7523429 | System for designing integrated circuits with enhanced manufacturability A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global des... | 04/21/2009 |
| 7512922 | Methods of structured placement of a circuit design A method of creating relatively placed macros (RPMS) for a circuit design for a target device can include determining N best configurations for each of a plurality of connections of the circuit design, wherein each configuration specifies relative positioning of a s... | 03/31/2009 |
| 7512921 | Method and apparatus for designing integrated circuit enabling the yield of integrated circuit to be improved by considering random errors A layout method in a layout apparatus for layout of an integrated circuit includes placing a plurality of cells at approximate positions according to the circuit data and placing the plurality of cells at specific positions according to the result of the placement o... | 03/31/2009 |
| 7509612 | Method of designing semiconductor chip and program for use in designing semiconductor chip Upon designing a standard cell type semiconductor chip, there are prepared a plurality of types of standard cells and a plurality of types of yield improvement standard cells having the same function as the standard cells and having a layout which is changed to impr... | 03/24/2009 |
| 7493581 | Analytical placement method and apparatus Some embodiments provide an analytical placement method that considers diagonal wiring. This method formulates an objective function that accounts for the use of diagonal wiring during routing. Some embodiments use horizontal, vertical, and ±45° diagonal lines. Fo... | 02/17/2009 |
| 7493582 | Pattern layout and layout data generation method A transistor layout including a diffusion region and a gate line. The gate line intersects part of the diffusion region in an overlapping manner. The layout includes an L-shaped bent portion included in the diffusion region. An auxiliary pattern is included in the d... | 02/17/2009 |
| 7475373 | Method and apparatus to visually assist legalized placement with non-uniform placement rules Embodiments of the present invention provide systems, methods and articles of manufacture for displaying semiconductor components in a graphical user interface and manipulating the position of semiconductor components. Embodiments of the present invention may check ... | 01/06/2009 |
| 7467369 | Constrained detailed placement The illustrative embodiments provide a computer implemented method which perform cell transforms that decrease overall wire length, without degrading device timing or violating electrical constraints. The process computes delay constraint coefficients for a data set... | 12/16/2008 |
| 7458051 | ECO cell for reducing leakage power A semiconductor structure including at least one spare cell is disclosed. The semiconductor structure includes a first conductive line coupled to a power supply, and a second conductive line coupled to a complementary power supply. At least one spare cell is decoupl... | 11/25/2008 |
| 7444610 | Visualizing hardware cost in high level modeling systems Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the cir... | 10/28/2008 |
| 7444609 | Method of optimizing customizable filler cells in an integrated circuit physical design process A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit... | 10/28/2008 |
| 7444605 | Generating a base curve database to reduce storage cost An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set id... | 10/28/2008 |
| 7441218 | Contact resistance and capacitance for semiconductor devices A method generates a design layout for an integrated circuit. A design is provided for an integrated circuit. Library cells are selected according to the design. The library cells are mapped into a chip area map. Unmapped cells are filled with filler cells. Critical... | 10/21/2008 |
| 7437690 | Method for predicate-based compositional minimization in a verification environment A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more output equivalent state sets are generated from the one or more output f... | 10/14/2008 |
| 7434187 | Method and apparatus to estimate delay for logic circuit optimization Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first ... | 10/07/2008 |
