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| Number | Title | Issue Date |
| 7895544 | Method to graphically identify registers with unbalanced slack as part of placement driven synthesis optimization A method for identifying latches in physical designs with unbalanced slack, comprising: creating a netlist describing a logical design, the logical design having a plurality of latches therein; performing a placement of the logical design to obtain a physical design... | 02/22/2011 |
| 7882475 | Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectors A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of o... | 02/01/2011 |
| 7849431 | CMOS inverter layout for increasing effective channel length Provided is a complementary metal oxide semiconductor (CMOS) inverter layout for increasing an effective channel length. The CMOS inverter layout may include first and second conductive MOS transistors respectively formed in first and second active regions, metal li... | 12/07/2010 |
| 7840926 | Layout schemes and methods of power gating transistor switches, semiconductor devices including the power gating transistor switches, and power gating methods of the semiconductor devices A semiconductor device may include a logic circuit and one or more power gating transistor switches. The logic circuit may be connected between a power voltage and a ground voltage, and may perform one or more logic operations. The one or more power gating transisto... | 11/23/2010 |
| 7836420 | Integrated circuit system with assist feature An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non... | 11/16/2010 |
| 7818701 | Memory controller with variable zone size Disclosed is a method of partitioning a memory, comprising dividing the memory into a first plurality of sub-zones, allocating a plurality of spare blocks in each of the first plurality of sub-zones, resizing the first plurality of sub-zones to a second plurality of... | 10/19/2010 |
| 7818702 | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates Device structure embodied in a machine readable medium for designing, manufacturing, or testing a design in which the design structure includes latch-up resistant devices formed on a hybrid substrate. The hybrid substrate is characterized by first and second semicon... | 10/19/2010 |
| 7752586 | Design structure of an integration circuit and test method of the integrated circuit A design structure for an integrated circuit which includes: a first flip-flop which is capable of flushing and which operates by using a first clock signal CLK 1; a second flip-flop DFF 2 which operates by using a second clock signal CLK 2, and... | 07/06/2010 |
| 7735040 | Method for designing cell layout of a semiconductor integrated circuit with logic having a data flow With a conventional method for designing cell layout, it is necessary to give relative positional information in advance to all cells to be arranged. Furthermore, the method is troublesome because it is necessary to correct relative positional information of cells a... | 06/08/2010 |
| 7730439 | Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically b... | 06/01/2010 |
| 7725857 | Method for optimizing organizational floor layout and operations A computer-automated method for analyzing an organizational floorplan layout, and making recommendations for modifying the layout to optimize productivity, and efficiency of operations conducted within the modified layout includes the following method steps. Gatheri... | 05/25/2010 |
| 7725858 | Providing a moat capacitance In one embodiment, the present invention includes an apparatus having core logic formed on a die, input/output (IO) buffers surrounding the core logic, and a moat capacitance surrounding the IO buffers and extending to an edge of the die. Other embodiments are descr... | 05/25/2010 |
| 7721238 | Method and apparatus for configurable printed circuit board circuit layout pattern A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit top... | 05/18/2010 |
| 7712064 | Manufacturing aware design of integrated circuit layouts Some embodiments of the invention provide a manufacturing aware process for designing an integrated circuit (“IC”) layout. The process receives a manufacturing configuration that specifies a set of manufacturing settings for a set of machines to be used to manuf... | 05/04/2010 |
| 7712065 | Automatic layout method and automatic layout device An automatic layout method for performing an automatic layout of components on a diagram, the automatic layout method includes: generating a layout engine control object based on an operation of an application program; selecting at least one layout engine object fro... | 05/04/2010 |
| 7707532 | Techniques for grouping circuit elements into logic blocks Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is ... | 04/27/2010 |
| 7698676 | Method and system for improving manufacturability of integrated devices A method and system for improving the yield of integrated devices by adaptively selecting contact and via sizes is described. According to this invention, the drawn size of via holes in a design layout is selected based on its adjacent geometry objects. The inventio... | 04/13/2010 |
| 7689960 | Programmable via modeling A method for verifying library components and designs on a via customizable ASIC, which may include the process of adding capacitors to model possible via sites of a model of an un-customized portion of or a whole ASIC, and replacing the capacitors with resistors to... | 03/30/2010 |
| 7681163 | Capacitor layout technique for reduction of fixed pattern noise in a CMOS sensor A new capacitor architecture includes a front plate of the capacitor formed from a first polysilicon layer. The front plate is surrounded by a first dielectric layer and a second dielectric layer. The back plate of the capacitor is formed from one layer of a first t... | 03/16/2010 |
| 7681164 | Method and apparatus for placing an integrated circuit device within an integrated circuit layout A system that places an integrated circuit (IC) device within an IC chip layout is presented. During operation, the system receives the IC device to be placed within the IC chip layout, wherein the IC chip layout includes one or more continuous rows of diffusion. Ne... | 03/16/2010 |
| 7669159 | IC tiling pattern method, IC so formed and analysis method The invention provides a method for providing an integrated circuit (6) having a substantially uniform density between parts (10, 12, 14 and 16) of the IC that are non-orthogonally angled. In particular, the invention provides fill tiling patter... | 02/23/2010 |
| 7669158 | Method and system for semiconductor design hierarchy analysis and transformation A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accompli... | 02/23/2010 |
| 7665054 | Optimizing circuit layouts by configuring rooms for placing devices A computer-readable medium stores a specification for a circuit layout. The specification includes: a configuration of rooms for placing devices, one or more room constraints for the configuration of rooms, one or more groups of devices for the rooms, and one or mor... | 02/16/2010 |
| 7657857 | Performance visualization of delay in circuit design Methods are provided for presenting delay characteristics of a circuit design. The methods acquire routing delay data and logic delay data for each of a number of paths within the circuit design. In one method, a scatterplot of the routing delay data versus the logi... | 02/02/2010 |
| 7624365 | Semiconductor integrated device and apparatus for designing the same A semiconductor integrated device includes a plurality of power system circuit units, a first circuit unit to which electric power is supplied from first power supply wiring, and first ground wiring to which the first circuit unit is coupled. Moreover, the semicondu... | 11/24/2009 |
| 7603641 | Power/ground wire routing correction and optimization A PG wire routing optimization tool for more efficiently routing PG wires in a layout design of an integrated circuit. The PG wire routing optimization tool analyzes a routing of the wires of a power and ground network for unacceptable IR-drops or electromigration p... | 10/13/2009 |
| 7590959 | Layout system, layout program, and layout method for text or other layout elements along a grid A system is provided that sets reference points or lines in a layout region and arranges a layout element in the layout region using the positions of the reference points or lines as reference positions. The system includes: a unit storing reference position informa... | 09/15/2009 |
| 7581202 | Method for generation, placement, and routing of test structures in test chips A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a given pad a... | 08/25/2009 |
| 7577931 | Semiconductor device and method of manufacturing the same A semiconductor device has power supply pads including a first power supply pad and at least one second power supply pad that are connected to internal power supply wirings through an internal circuit so that the first and second power supply pads are set to the sam... | 08/18/2009 |
| 7543259 | Method and device for deciding support portion position in a backup device A host computer 80 for wholly controlling an electronic component mounting line displays a surface side image and a reverse side image which respectively show a surface side and a reverse side of a board having components mounted thereon, with the images bein... | 06/02/2009 |
| 7539962 | Pattern data correcting method, photo mask manufacturing method, semiconductor device manufacturing method, program and semiconductor device There is provided a method of correcting pattern data for a semiconductor device, including acquiring pattern data for a lower layer, pattern data for an upper layer, and pattern data for a connecting layer containing connecting patterns to connect patterns containe... | 05/26/2009 |
| 7516434 | Layout design program, layout design device and layout design method for semiconductor integrated circuit A computer program product for floorplanning design of a semiconductor integrated circuit, embodied on a computer-readable medium and including code that, when executed, causes a computer to perform the following steps (a) to (d). The step (a) is the step of placing... | 04/07/2009 |
| 7500211 | Unit cell of semiconductor integrated circuit and wiring method and wiring program using unit cell A unit cell of a semiconductor integrated circuit capable of improving wiring efficiency in layout of a functional circuit block or the like using a unit cell, and a wiring method and wiring program using the unit cell are provided. In a unit cell, auxiliary power w... | 03/03/2009 |
| 7496877 | Electrostatic discharge failure avoidance through interaction between floorplanning and power routing An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints ... | 02/24/2009 |
| 7469396 | Semiconductor device and layout design method therefor A layout design method for a semiconductor device includes a step of arranging transistors, a dummy gate forming step of forming dummy gates, which has a shape identical with a shape including gate electrodes or the gate electrodes and projected parts from active re... | 12/23/2008 |
| 7469397 | Automatic trace determination method and apparatus for automatically determining optimal trace positions on substrate using computation An automatic trace determination apparatus for automatically determining optimal positions of traces from pads to corresponding vias on a substrate using computation comprises: tentative determination means for tentatively determining a tentative target line with wh... | 12/23/2008 |
| 7464356 | Method and apparatus for diffusion based cell placement migration A method for cell placement in an integrated circuit design that uses a calculated diffusion velocity determined from a density value in order to relocate the cells until the cell placement reduces the density below a predetermined threshold. The method acts to cont... | 12/09/2008 |
| 7444610 | Visualizing hardware cost in high level modeling systems Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the cir... | 10/28/2008 |
| 7444609 | Method of optimizing customizable filler cells in an integrated circuit physical design process A system and method for optimizing customizable filler cells in an integrated circuit physical design process. In particular, a filler cell placement algorithm of the present disclosure is utilized in the method to optimize the customizable filler cells in a circuit... | 10/28/2008 |
| 7441208 | Methods for designing integrated circuits The process of designing an integrated circuit (“IC”) to implement a generalized circuit design includes a signoff between a front-end part of the process and a back-end part of the process. This signoff preferably takes place after at least some global routing ... | 10/21/2008 |
