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| Number | Title | Issue Date |
| 8086972 | Functional verification of power gated designs by compositional reasoning A novel and useful method of functional verification of power gated designs by compositional reasoning. The method of the present invention performs a sequential equivalence check between the power gated design and a version of itself in which power gating is disabl... | 12/27/2011 |
| 7913194 | Systems and methods for super-threading In one embodiment of the invention, a method is disclosed including receiving a netlist of an integrated circuit design; executing a first copy of an integrated circuit design program with a first processor associated with a first memory space to independently perfo... | 03/22/2011 |
| 7904848 | System and method for runtime placement and routing of a processing array A system for mapping tasks of at least one application on processing units of a reconfigurable array, the system comprising a plurality of programmable processing units, each programmable processing unit having at least one connection node, the programmable processi... | 03/08/2011 |
| 7873927 | Partitioning a large design across multiple devices A method of partitioning a design across a plurality of integrated circuits can include creating a software construct for each one of the plurality of integrated circuits and assigning a plurality of instances to a selected software construct. Each of the plurality ... | 01/18/2011 |
| 7836419 | Method and system for partitioning integrated circuits Method and system for partitioning integrated circuits are disclosed. The method includes receiving a netlist representation of the circuit comprising circuit components, partitioning the circuit to form one or more circuit partitions according to a predefined parti... | 11/16/2010 |
| 7827511 | Power distribution network of an integrated circuit An integrated circuit (51) comprises a power distribution network having a power pad (53) and a ground pad (55) arranged at diagonally opposite corners of the integrated circuit (51). A power bus (67, 69) and a ground bus (71, 7... | 11/02/2010 |
| 7823110 | Method and system for processing geometrical layout design data A method and system for processing geometrical layout design data in a computation network. The method includes assigning one or more partitions of the geometrical layout design data to one or more computing devices. One or more partitions are assigned based on firs... | 10/26/2010 |
| 7814452 | Function symmetry-based optimization for physical synthesis of programmable integrated circuits A computer-implemented method of technology mapping a circuit design for implementation within a programmable logic device can include determining a plurality of cut sets for the circuit design, wherein each cut set includes a plurality of cuts. The method can inclu... | 10/12/2010 |
| 7797659 | Analog/digital partitioning of circuit designs for simulation For increasing user control and insight into preparing a mixed-signal semiconductor design specification for simulation, there are provided methods responsive to commands that provide control over resolution of disciplines and partitioning of the design into analog ... | 09/14/2010 |
| 7788618 | Scalable dependent state element identification Methods, systems and software products are provided to enhance the scalability of dependent state analysis element identification. In a method of partitioning a model representing a state machine, a variable is selected from the variables of the model, and a first s... | 08/31/2010 |
| 7761828 | Partitioning electronic circuit designs into simulation-ready blocks A partitioning method for an integrated circuit (IC) design includes providing a textual file representing the design as library-specific cells and interconnections, including timing data for the cells and timing data derived from the design after placement and rout... | 07/20/2010 |
| 7730438 | Methods and apparatuses for designing multiplexers Methods and apparatuses for designing multiplexers in one or more integrated circuits are described. One exemplary method includes receiving a representation of a first multiplexer and converting the representation to a partition neutral representation of the first ... | 06/01/2010 |
| 7725856 | Method and apparatus for performing parallel slack computation A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. Chunks are identified from the domains and sub-domain. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed.... | 05/25/2010 |
| 7703059 | Method and apparatus for automatic creation and placement of a floor-plan region A method and apparatus for floor-plan region creation and placement is provided. Design information may be received. Module area may be estimated for each module in an integrated circuit. Individual module may be selected for regioning, and region size and dimension... | 04/20/2010 |
| 7703060 | Stitched IC layout methods, systems and program product Stitched integrated circuit (IC) chip layout methods, systems and program products are disclosed. In one embodiment, a method includes obtaining from a first entity a circuit design for an IC chip layout that exceeds a size of a photolithography tool field at a seco... | 04/20/2010 |
| 7703061 | IC design modeling allowing dimension-dependent rule checking A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals... | 04/20/2010 |
| 7698675 | Method and design system for semiconductor integrated circuit with a reduced placement area A standard cell is split into a plurality of regions, and shareability information having pin information is added to a cell library for each of the split regions. Through comparison of shareability information, a determination is made as to whether, at the time of ... | 04/13/2010 |
| 7694256 | Method and apparatus for performing analytic placement techniques on logic devices with restrictive areas A method for designing a system on a target device having restricted areas includes determining locations on the target device for all cells in the system by solving one or more equations. Partitioning of cells of a first classification type is performed. One or mor... | 04/06/2010 |
| 7689959 | Code generator for finite state machines The present invention relates to a method for automatically generating HDL code, a code generator and a product for generating the code for the purpose of its implementation in programmable logic, based on a graphical representation for coding a state machine. With ... | 03/30/2010 |
| 7689958 | Partitioning for a massively parallel simulation system A method involves building an intermediate form data flow graph (IFgraph) from an intermediate form data flow tree (IFtree) associated with the logic design, partitioning the IFgraph across at least three levels of granularity to obtain a partitioned IFgraph, wherei... | 03/30/2010 |
| 7681162 | Standard cell, cell library using a standard cell and method for arranging via contact According to an aspect of the present invention, there is provided a standard cell, including a cell frame having a rectangular region, a power supply interconnection, a center line of the power supply interconnection overlapping with a side line along a first direc... | 03/16/2010 |
| 7669157 | Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches A method for designing a system on a target device includes merging a netlist for a first partition of the system generated from a bottom-up design flow with a netlist for a second partition of the system from a top-down design flow to form a combined netlist, and p... | 02/23/2010 |
| 7657856 | Method and system for parallel processing of IC design layouts Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where ... | 02/02/2010 |
| 7607117 | Representing device layout using tree structure Methods are described herein for using a tree structure representation for searching selected areas of a programmable device layout in order to determine the existing component configuration of a device. The tree structure may be generated by assigning root nodes, b... | 10/20/2009 |
| 7603640 | Multilevel IC floorplanner To generate a floorplan for an integrated circuit to be formed by a collection of modules interconnected by nets, the floorspace to be occupied by the integrated circuit is partitioned into regions and all of the modules are allocated among those regions. The region... | 10/13/2009 |
| 7584444 | System and method for external-memory graph search utilizing edge partitioning A method and system is provided for generator successor nodes in an external-memory search of a graph having a plurality of nodes and outgoing edges of the plurality of nodes. The method and system includes construction of an abstract representation of the graph to ... | 09/01/2009 |
| 7568176 | Method, system, and computer program product for hierarchical integrated circuit repartitioning A method, system, and computer program product for hierarchical integrated circuit repartitioning are provided. The method includes receiving parent level placement data for one or more interconnecting elements and designating at least one child to receive a pushdow... | 07/28/2009 |
| 7562325 | Device to cluster Boolean functions for clock gating A system for clustering Boolean functions for clock gating according to various exemplary embodiments can include a computer configured to identify at least two small gating groups within a clock tree representative of an electrical network and at least two gating f... | 07/14/2009 |
| 7516433 | Non-orthogonal structures and space tiles for layout, placement, and routing of an integrated circuit Disclosed is an improved approach for maintaining the structures for objects in a layout. A single type of structure is maintained that can be used to store or track a polygon of any shape, as long as the shape possesses a supported number of sides. The structure is... | 04/07/2009 |
| 7509611 | Heuristic clustering of circuit elements in a circuit design An apparatus, program product and method utilize heuristic clustering to generate assignments of circuit elements to clusters or groups to optimize a desired spatial locality metric. For example, circuit elements such as scan-enabled latches may be assigned to indiv... | 03/24/2009 |
| 7478352 | Method for creating box level groupings of components and connections in a dynamic layout system A system and method for automatically generating a dynamic layout of a top-level canvas with an internal box layout structure providing a storage element, and a processing element capable of receiving requests to assign a plurality of components within the canvas; a... | 01/13/2009 |
| 7478351 | Designing system and method for designing a system LSI A method for designing a system LSI includes the steps of dividing an algorithmic description (D1) of the system LSI into software and hardware groups, synthesizing the hardware group by behavior synthesis to create an RTL description ((D5) and a simul... | 01/13/2009 |
| 7467367 | Method and system for clock tree synthesis of an integrated circuit Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit. The block-level clock tree structure is estimated based on a grid-bas... | 12/16/2008 |
| 7467368 | Circuit clustering during placement A method of physical circuit design can include the steps of packing components of a circuit design that are dependent upon an architecture of the circuit design and assigning initial locations to each component of the circuit design. The components of the circuit d... | 12/16/2008 |
| 7458050 | Methods to cluster boolean functions for clock gating A method to cluster Boolean functions for clock gating according to various exemplary embodiments can include identifying at least two small gating groups within a clock tree representative of an electrical network and at least two gating functions of the at least t... | 11/25/2008 |
| 7454732 | Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a hierarchical resource estimation is performed based on a technology indep... | 11/18/2008 |
| 7444275 | Multi-variable polynomial modeling techniques for use in integrated circuit design Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage s... | 10/28/2008 |
| 7444277 | Facilitating simulation of a model within a distributed environment Simulation of models within a distributed environment is facilitated. A model is partitioned based on clock domains, and communication between partitions on different processors is performed on synchronous clock boundaries. Further, data is exchanged across the netw... | 10/28/2008 |
| 7437691 | VLSI artwork legalization for hierarchical designs with multiple grid constraints A system and method are disclosed for legalizing a flat or hierarchical VLSI layout to meet multiple grid constraints and conventional ground rules. Given a set of ground rules with multiple grid constraints and a VLSI layout (either hierarchical or flat) which is l... | 10/14/2008 |
| 7434185 | Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of inter... | 10/07/2008 |
