Class 716/6 - Timing analysis (e.g., delay time, path delay, latch timing)

Subclass of Class 716 - Data processing: design and analysis of circuit or semiconductor mask
Definition: Subject matter wherein the design verification is confirmed
No. of patents: 2127
Last issue date: 01/24/2012

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Number	Title	Issue Date
8103975	Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a se...	01/24/2012
7930652	Timing circuit CAD A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprise steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line del...	04/19/2011
7925998	Delay calculating method in semiconductor integrated circuit An input pin capacitance of a cell is obtained in advance in a function expression, and a delay is calculated in such manner that the input pin capacitance is calculated in functions of an input slew and a drive load capacitance in each instance. In a cell character...	04/12/2011
7890905	Slew constrained minimum cost buffering A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew ar...	02/15/2011
7890904	Estimating jitter in a clock tree of a circuit and synthesizing a jitter-aware and skew-aware clock tree In one embodiment, a method for computing jitter in a clock tree includes dividing a clock tree into a plurality of stages and computing jitter in one or more of the stages according to a model of at least a portion of a circuit associated with the clock tree. The m...	02/15/2011
7886247	Method and apparatus for statistical path selection for at-speed testing In one embodiment, the invention is a method and apparatus for statistical path selection for at-speed testing. One embodiment of a method for selecting a path of an integrated circuit chip for at-speed testing includes computing a process coverage metric for a plur...	02/08/2011
7886245	Structure for optimizing the signal time behavior of an electronic circuit design A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. T...	02/08/2011
7886246	Methods for identifying failing timing requirements in a digital design Methods for identifying failing timing requirements in a digital design. The method includes identifying at least one timing test in the digital design that has a passing slack in a base process corner and a failing slack in a different process corner. The method fu...	02/08/2011
7882472	Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis process In the course of unit timing, there exists the possibility for a non-compute (N/C) on a particular net in an IC chip design, which could be caused by numerous things, including but not limited to a pin being tied to power, a floating output, or invalid timing test f...	02/01/2011
7882473	Sequential equivalence checking for asynchronous verification Mechanisms for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossing...	02/01/2011
7882471	Timing and signal integrity analysis of integrated circuits with semiconductor process variations In one embodiment of the invention, a method of statically analyzing an integrated circuit with process and environment variations is provided. The method includes characterizing each circuit cell of a cell library for a sensitivity to process parameter variations w...	02/01/2011
7882474	Testing phase error of multiple on-die clocks The phase relationship between two clock signals in an integrated circuit (IC) is determined by transforming each of the clock signals into a data word, where bit transitions in the data word represent signal transitions in the clock signal, and comparing the two da...	02/01/2011
7873926	Methods for practical worst test definition and debug during block based statistical static timing analysis Methods for analyzing timing of an integrated circuit using block-based static statistical timing analysis and for practical worst test definition and debug. The method includes building a timing graph, determining a slack for each of the nodes in the timing graph, ...	01/18/2011
7870525	Slack sensitivity to parameter variation based timing analysis A method, system and program product are disclosed for improving an IC design that prioritize failure coefficients of slacks that lead to correction according to their probability of failure. With an identified set of independent parameters, a sensitivity analysis i...	01/11/2011
7865856	System and method for performing transistor-level static performance analysis using cell-level static analysis tools A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static performance analysis on a circuit represented by a transistor level netlist. The method begins with converting said transistor-level netlist to a cell-level...	01/04/2011
7865855	Method and system for generating a layout for an integrated electronic circuit A method for generating a layout for an integrated circuit having a plurality of sinks and at least one source is disclosed. The source supplies a plurality of signals to the respective plurality of sinks. The method includes: identifying the source which supplies a...	01/04/2011
7861198	Distorted waveform propagation and crosstalk delay analysis using multiple cell models A method to perform timing analysis for a complex logic cell with distorted input waveform and coupled load networks is presented. Timing arc based models are used in conjunction with CCB based current models of portions of the logic cell to compute the output signa...	12/28/2010
7861201	Method for verifying timing of a circuit with crosstalk victim and aggressor A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating b...	12/28/2010
7861200	Setup and hold time characterization device and method A method of characterizing a device under test (DUT) includes determining a goal function associated with a setup and hold time for the DUT. A minimum value for the goal function is determined by iteratively adjusting setup and hold times for input data to the DUT, ...	12/28/2010
7861199	Method and apparatus for incrementally computing criticality and yield gradient In one embodiment, the invention is a method and apparatus for incrementally computing criticality and yield gradient. One embodiment of a method for computing a diagnostic metric for a circuit includes modeling the circuit as a timing graph, determining a chip slac...	12/28/2010
7853911	Method and apparatus for performing path-level skew optimization and analysis for a logic design A method for designing a system including optimizing path-level skew in the system and analyzing path-level skew in the system. Other embodiments are also disclosed. ...	12/14/2010
7853912	Arrangements for developing integrated circuit designs In some embodiments, a method is disclosed for converging on an acceptable integrated circuit design for an integrated circuit. The method can include selecting a path, determining if the path has a timing deficiency, segmenting the path into path segments and alloc...	12/14/2010
7849430	Reverse donut model A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified...	12/07/2010
7849429	Methods for conserving memory in statistical static timing analysis A method is provided for memory conservation in statistical static timing analysis. A timing graph is created with a timing run in a statistical static timing analysis program. A plurality of nodes in the timing graph that are candidates for a partial store and cons...	12/07/2010
7844933	Methods of optimizing timing of signals in an integrated circuit design using proxy slack values A method of optimizing timing of signals within an integrated circuit design using proxy slack values propagates signals through the integrated circuit design to output timing signals. For early mode timing analysis, the method sets an early proxy slack value to zer...	11/30/2010
7844931	Method and computer system for optimizing the signal time behavior of an electronic circuit design A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected ...	11/30/2010
7844932	Method to identify timing violations outside of manufacturing specification limits A method of evaluating an integrated circuit design selects manufacturing parameters of interest which are outside of manufacturing specification limits. Then, the method runs timing tests on the integrated circuit design and successively evaluates the timing test r...	11/30/2010
7840925	Source specific timing checks on synchronous elements using a static timing analysis engine A computer-implemented method of performing timing analysis upon a circuit design having synchronous circuit elements can include selecting a destination pin having a plurality of source pins, wherein each source pin of the plurality of source pins defines a data pa...	11/23/2010
7840924	Apparatus, method, and program for verifying logic circuit operating with multiple clock signals A verification apparatus that can verify a circuit in a shorter time while taking possible metastability into consideration. A clock domain crossing (CDC) detector finds CDC paths between circuit elements operating with different clocks in the circuit. A delay gener...	11/23/2010
7840923	Methods and apparatuses for designing integrated circuits using virtual cells Methods and apparatuses for analyzing and/or designing integrated circuits using virtual transparent cells disclosed. Some embodiments comprise calculating model values for virtual transparent cells or elements of an integrated circuit design varying a transparency ...	11/23/2010
7836418	Method and system for achieving power optimization in a hierarchical netlist The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a pl...	11/16/2010
7836417	Method and apparatus for parallel carry chains An apparatus having two or more parallel carry chain structures, each of the carry chain structures comprising a series of logical structures, where at least one of the logical structures within each of the carry chain structures has an associated input node, output...	11/16/2010
7831945	Manufacturing a clock distribution network in an integrated circuit A method of designing a clock distribution network in an integrated circuit, the method including: creating a clock distribution network with all cells having a maximum drive strength; supplying parameters of the clock distribution network to a timing analysis tool;...	11/09/2010
7831946	Clock distribution network wiring structure A wiring structure for clock signals has two or more parallel clock signal wires disposed in adjacent power wire bays that span the distance between the sinks to which the clock signal wires are to be coupled. The parallel clock signal wires are shorted one to anoth...	11/09/2010
7823107	Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design An embodiment of a design structure is shown for noise reduction comprising synthesizing blocks of sequential latches, e.g., a pipeline circuit architecture or clocking domain, which comprises combinational logic, synthesizing a root or a master clock and at least o...	10/26/2010
7823108	Chip having timing analysis of paths performed within the chip during the design process An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the...	10/26/2010
7818699	Dynamic core pipeline A circuit configuration for a pipeline core to be implemented in a programmable integrated circuit (IC) is dynamically specified by providing a single code set embodying an expanded netlist representative of a dynamic circuit configuration of the pipeline core. The ...	10/19/2010
7818700	System and method for verification and generation of timing exceptions The invention relates to a method for verifying one or more exceptions in a logic circuit comprising the steps of: a first step of providing an initial representation of a logic circuit; a second step of indicating at least one exception for the logic circuit; a thi...	10/19/2010
7814450	Active skew control of a digital phase-lock loop using delay lock-loops Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the ...	10/12/2010
7814451	Incremental relative slack timing force model Simultaneous Dynamical Integration modeling techniques are applied to global placement of elements of integrated circuits as described by netlists specifying interconnection of morphable-devices. Solutions to a system of coupled ordinary differential equations in ac...	10/12/2010

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Class 716/6 - Timing analysis (e.g., delay time, path delay, latch timing)