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| Number | Title | Issue Date |
| 7904847 | CMOS circuit leakage current calculator This invention provides a method for determining leakage current in a CMOS circuit having several devices. It includes the steps of reading a netlist which describes the circuit and includes information on both these devices in the circuit and how these devices are ... | 03/08/2011 |
| 7904846 | Method for automatically extracting a functional coverage model from a constraint specification A computer is programmed to automatically generate in memory, goals for functional verification of a design of a circuit by use of constraints that are specified in the normal manner. Specifically, a predetermined set of rules are automatically applied to the constr... | 03/08/2011 |
| 7895543 | Method for verifying timing of a circuit with RLC inputs and outputs A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating b... | 02/22/2011 |
| 7890901 | Method and system for verifying the equivalence of digital circuits The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding... | 02/15/2011 |
| 7890903 | Method and system for formal verification of an electronic circuit design A new and convenient methodology for proving the correctness of multiplier and multiply-accumulate circuit designs in a full custom design flow. Such an approach utilizes a basic description of the implemented algorithm, which is created in early phases of the desig... | 02/15/2011 |
| 7890902 | Methods and apparatus for merging coverage for multiple verification and design scenarios A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive ... | 02/15/2011 |
| 7886243 | System and method for using rules-based analysis to enhance models-based analysis The present invention presents a hybrid approach for manufacturability analysis that integrates both a rules-based approach and a models-based approach. For example, a rules-based analysis can be used to optimize the performance of a model-based analysis. The rules ... | 02/08/2011 |
| 7886244 | Driving values to DC adjusted/untimed nets to identify timing problems An apparatus and computer program product for driving values to “don't care” (DC) adjusted/untimed nets of an integrated circuit design to thereby identify timing problems are provided. The apparatus and computer program product may be utilized, for example, wit... | 02/08/2011 |
| 7886242 | Systems, methods, and apparatus for total coverage analysis and ranking of circuit designs In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed ... | 02/08/2011 |
| 7882469 | Automatic verification of adequate conductive return-current paths After finding the shortest conductive signal return-current path for each signal, the invention assesses whether each conductive return-current path is adequate. The method analyzes each shortest conductive signal return-current path and determines if a significant ... | 02/01/2011 |
| 7882470 | Method for heuristic preservation of critical inputs during sequential reparameterization A method, system, and computer program product for preserving critical inputs. According to an embodiments of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated... | 02/01/2011 |
| 7882468 | Integrated circuit device evaluation device, evaluation method, and evaluation program Time-axis data that include the peak waveform and the clock frequency of the power supply current when the LSI is switched are inputted to the LSI information input unit, and the LSI equivalent circuit creation unit creates an equivalent circuit of the LSI on the ba... | 02/01/2011 |
| 7877717 | Accurately modeling an asynchronous interface using expanded logic elements Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanis... | 01/25/2011 |
| 7870523 | System and method for test generation with dynamic constraints using static analysis and multidomain constraint reduction The present invention provides a system and method for resolving a test generation problem involving constraint resolution problems where a verification environment includes constraints that are suitable for resolution using one type of solver for a first domain and... | 01/11/2011 |
| 7870524 | Method and system for automating unit performance testing in integrated circuit design A method and system for automating unit performance testing in integrated circuit design is disclosed. One embodiment of the present invention sets forth a method, which includes the steps of generating a first performance data for the unit to operate on a workload,... | 01/11/2011 |
| 7865853 | Systems, methods, and media for block-based assertion generation, qualification and analysis Systems, methods, and media for block-based assertion generation, qualification and analysis are disclosed. Embodiments may include a method for generating assertions for verifying a design. The embodiment may include generating session preferences, the session pref... | 01/04/2011 |
| 7865854 | Simultaneous parameter-driven and deterministic simulation with or without synchronization A method for allowing simultaneous parameter-driven and deterministic simulation during verification of a hardware design, comprising: enabling a plurality of random parameter-driven commands from a random command generator to execute in a simulation environment dur... | 01/04/2011 |
| 7865851 | Capacitance extraction of intergrated circuits with floating fill The present invention improves the accuracy of parasitic capacitance extraction of IC designs with floating fill. One embodiment of the present invention approximates the coupling capacitances of fill nets beyond an exact-approximation level by a fill net eliminatio... | 01/04/2011 |
| 7865852 | Method for automatically routing multi-voltage multi-pitch metal lines A method for program routing a circuit with at least a first and second voltages in a single layer is disclosed, which comprises defining a first and second layer types corresponding to the first and second voltages, respectively, specifying at least one first attri... | 01/04/2011 |
| 7861197 | Method of verifying design of logic circuit A method of verifying a design of logic circuit of a semiconductor device having a first circuit block to which the power continuously applied and a second circuit block receiving the power which turns on/off in response to the state of operation modes includes repl... | 12/28/2010 |
| 7856609 | Using constraints in design verification A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state... | 12/21/2010 |
| 7853906 | Accelerating high-level bounded model checking An accelerated High-Level Bounded Model Checking method that efficiently extracts high-level information from the model, uses that extracted information to obtain an improved verification model, and applies relevant information on-the-fly to simplify the BMC-problem... | 12/14/2010 |
| 7853907 | Over approximation of integrated circuit based clock gating logic A novel method for optimizing the implementation of clock gating logic in digital circuits utilizing clock gating. The method over-approximates the clock gating function by removing the variable with the least influence on the resulting approximation function. Appro... | 12/14/2010 |
| 7853908 | Algorithmic reactive testbench for analog designs An Algorithmic Reactive Testbench (ART) system is provided for the simulation/verification of an analog integrated circuit design. The ART system is a high level simulation/verification environment with a user program in which one or more analog testbenches are inst... | 12/14/2010 |
| 7853909 | ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device An ESD (Electrostatic Discharge) analysis device includes: a circuit simulation unit; a border cell extraction unit; and a check unit. The circuit simulation unit executes a circuit simulation of design data of a semiconductor integrated circuit including a pluralit... | 12/14/2010 |
| 7853910 | Parasitic effects analysis of circuit structures Method, system, and computer program product for analyzing circuit structures for parasitic effects are provided. Data from a previous parasitic effect analysis of a circuit structure is used to perform parasitic effect analysis on another circuit structure even whe... | 12/14/2010 |
| 7849427 | Auto-router performing simultaneous placement of signal and return paths An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths ... | 12/07/2010 |
| 7849426 | Mechanism for detection and compensation of NBTI induced threshold degradation The embodiments of the invention provide a design structure for detection and compensation of negative bias temperature instability (NBTI) induced threshold degradation. A semiconductor device is provided comprising at least one stress device having a voltage applie... | 12/07/2010 |
| 7849428 | Formally deriving a minimal clock-gating scheme The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verific... | 12/07/2010 |
| 7844930 | Method and apparatus for circuit partitioning and trace assignment in circuit design Methods and apparatuses to design a circuit. In one embodiment, the method includes determining a first multiplexing ratio by a computer. The method, in one embodiment, further includes determining, according to the first multiplexing ratio, a first partition soluti... | 11/30/2010 |
| 7840922 | Semiconductor design support apparatus The semiconductor design support apparatus relating to the layout verification. For executing layout verification in high accuracy, the apparatus includes a unit for generating a recognition pattern in a region having a first axis of symmetry and a second axis of sy... | 11/23/2010 |
| 7836416 | Hardware-based HDL code coverage and design analysis Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with... | 11/16/2010 |
| 7831944 | Circuit-design supporting apparatus, circuit-design supporting method, computer product, and printed-circuit-board manufacturing method An FPGA-information managing unit included in a circuit-designing CAD apparatus retrieves FPGA information, such as pin-assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. When performing a DRC, as for in an FPGA, a ... | 11/09/2010 |
| 7831943 | Checking for valid slice packing in a programmable device A method of determining validity of slice packing for a programmable device can include identifying a slice topology for a slice, identifying a circuit fragment assigned to the slice, and generating a set of Boolean equations describing conditions for mapping the ci... | 11/09/2010 |
| 7831942 | Design check database Systems and methods for creating and implementing two-dimensional (2D), image-based design rules (IBDRs) are disclosed. Techniques for creating 2D IBDR can include identifying a search pattern that is representative of a 2D pattern of interest of a design, creating ... | 11/09/2010 |
| 7823104 | Determination of single-fix rectification function Some aspects provide determination of a function to rectify functional differences between netlist G1 and netlist G2 having inputs V. The determination may include determination of a signal s of netlist G1 that can be re-synthesized ... | 10/26/2010 |
| 7823106 | Variable performance ranking and modification in design for manufacturability of circuits A method, computer system and program product introduce adding a variable performance ranking parameter to a diagram of a circuit to drive implementation of modifications that are yield improving, performance boosting, or performance-neutral. The information is pair... | 10/26/2010 |
| 7823105 | Layout data generation equipment of semiconductor integrated circuit, data generation method and manufacturing method of semiconductor device A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logi... | 10/26/2010 |
| 7823103 | Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data A method and system for validating a design rule checking program. The method and system includes creating a hierarchal structure such that each layer of the hierarchal structure corresponds to a process layer of a device or subregion of a shape. The method and syst... | 10/26/2010 |
| 7814447 | Supplant design rules in electronic designs Disclosed is an improved method, system, and computer program product for electronic designs with supplant design rules. According to some embodiments of the invention, the foundry-imposed design rules are replaced by one or more supplant design requirements which d... | 10/12/2010 |
