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| Number | Title | Issue Date |
| 7430697 | Method of testing circuit blocks of a programmable logic device A method of testing circuits in a programmable logic device is described. According to one embodiment of the invention, a method comprises steps of configuring a configurable logic block of the programmable logic device with a test signal source and a logic circuit;... | 09/30/2008 |
| 7430729 | Design rule report utility This invention provides a graphical tool by which a person may quickly and efficiently check the relational information between elements of a computer model. The invention may be used to quickly validate the design rules, like minimum spacing requirements between th... | 09/30/2008 |
| 7428714 | Line width error check A method of checking for errors in line width in an integrated circuit includes identifying with a marker any lines having a line width greater than a minimum line width, and associating a line width parameter with each line width marker, the line width parameter co... | 09/23/2008 |
| 7428675 | Testing using independently controllable voltage islands A voltage island architecture wherein the source voltage of each voltage island can be independently turned on/off or adjusted during a scan-based test. The architecture includes a plurality of voltage islands (102, 104), each powered by a respective island s... | 09/23/2008 |
| 7428712 | Design optimization using approximate reachability analysis Aspects of computing design invariants, by using approximate reachability analysis, include reducing the circuit model for verification and synthesis. Further included is computing invariants using approximate reachability analysis to optimize a circuit model by ide... | 09/23/2008 |
| 7428715 | Hole query for functional coverage analysis Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set of non-covered events is specified. A coverage query is then automatic... | 09/23/2008 |
| 7428674 | Monitoring the state vector of a test access port Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitor... | 09/23/2008 |
| 7426461 | Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective pluralit... | 09/16/2008 |
| 7426668 | Performing memory built-in-self-test (MBIST) Programmable memory built-in self-test (MBIST) methods, apparatus, and systems are disclosed. Exemplary embodiments of the disclosed technology can be used, for example, to test one or more memories located on an integrated circuit during manufacturing testing. ... | 09/16/2008 |
| 7426705 | Combined hardware/software assertion checking Assertion checking is achieved by modifying a given set of assertions to include subsuming assertions that cover one or more of given assertions and also require less logic to implement, by implementing at least the subsuming assertions in functionally reconfigurabl... | 09/16/2008 |
| 7426704 | Design verification of highly optimized synchronous pipelines via random simulation driven by critical resource scheduling Testing a model of a logic circuit model. The testing includes generating valid random input stimulus sequences for a logic circuit model. Enumerating critical resource requirements, enumerating critical resource availabilities does this, and selecting of stimulus s... | 09/16/2008 |
| 7424690 | Interconnect integrity verification A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file... | 09/09/2008 |
| 7424417 | System and method for clock domain grouping using data path relationships A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of ea... | 09/09/2008 |
| 7421383 | Method for extracting and modeling semiconductor device series resistance and for simulating a semiconductor device with use thereof Semiconductor device junction simulation is carried out utilizing models that are developed with series resistance extractions that improve their fidelity particularly in the high current regions of device operation. The models may also be tailored to account for ge... | 09/02/2008 |
| 7421668 | Meaningful visualization of properties independent of a circuit design A property used in functional verification of a circuit design is debugged independently of the circuit design for which the property is intended. Visualization of the property under various conditions helps a user to debug any errors in how the property is implemen... | 09/02/2008 |
| 7421675 | Annotating timing information for a circuit design for increased timing accuracy A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the mini... | 09/02/2008 |
| 7421670 | Chip development system enabled for the handling of multi-level circuit design data A system and method for implementation of look-ahead design methodology. Efficient debugging of a design is accomplished by evaluating the high level register transfer level (RTL) representation of a device being designed by quickly simulating the downstream impleme... | 09/02/2008 |
| 7421674 | Apparatus and method for analyzing post-layout timing critical paths A critical path detecting unit for detecting critical paths for a design in which cells are placed on an integrated circuit and information concerning timing constraints. A representative-critical-path extracting unit extracts a representative critical path by havin... | 09/02/2008 |
| 7421667 | System and method for enabling a vendor mode on an integrated circuit A system and method for enabling a vendor mode on an integrated circuit. A method is disclosed for applying a potential to a no-connect pin, whose function is unknown to the customer, to prevent the accidental enabling of the vendor mode. Applying the potential to t... | 09/02/2008 |
| 7418603 | Mobile terminal, circuit board, circuit board design aiding apparatus and method, design aiding program, and storage medium having stored therein design aiding program The present invention provides a tamper resistant circuit board, an apparatus and method for aiding the design of the circuit board, a computer readable storage medium having stored therein a program for performing the method, and a mobile terminal containing the ci... | 08/26/2008 |
| 7418694 | Method for generating test patterns utilized in manufacturing semiconductor device A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a conditio... | 08/26/2008 |
| 7418688 | Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing ana... | 08/26/2008 |
| 7418681 | Simulation system, simulation method and simulation program for verifying logic behavior of a semiconductor integrated circuit A simulation system for verifying logic behavior of a semiconductor integrated circuit includes a reprogrammable semiconductor device having an interface circuit and a logic circuit; and an analyzing unit dividing a logic behavior of the semiconductor integrated cir... | 08/26/2008 |
| 7418680 | Method and system to check correspondence between different representations of a circuit A method to check correspondence between different representations of a circuit may include abstracting a first computer language representation of the circuit to form a first abstract model of the circuit and abstracting a second computer language representation of... | 08/26/2008 |
| 7418677 | Method of calculating predictive shape of wire structure, calculation apparatus, and computer-readable recording medium A calculating apparatus includes a finite element model creating unit that creates a finite element model of the wire structure, a setting unit that sets physical properties, restriction conditions and loads of the wire structure to the finite element model, a predi... | 08/26/2008 |
| 7418682 | Method and mechanism for performing DRC processing with reduced passes through an IC design A method and mechanism is disclosed for performing a spacing rule DRC check that does not require an excessive number of passes through the IC design. In one approach, a two-pass approach is employed to perform a spacing check. In an approach, a polygons are associa... | 08/26/2008 |
| 7415686 | Memory timing model with back-annotating A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data inp... | 08/19/2008 |
| 7415694 | Graph based phase shift lithography mapping method and apparatus For phase-shifting micro lithography, a method of assigning phase to a set of shifter polygons in a mask layer separated by a set of target features includes assigning a first phase to a first shifter polygon, identifying a set of target features that touch the firs... | 08/19/2008 |
| 7415680 | Power managers for an integrated circuit A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated ... | 08/19/2008 |
| 7415679 | System and method for selecting MOSFETs suitable for a circuit design The present invention provides a computer-based method for selecting MOSFETs suitable for a circuit design. The method includes the steps of: providing a database (18) that stores specifications and product information of various MOSFETs; receiving specificat... | 08/19/2008 |
| 7415684 | Facilitating structural coverage of a design during design verification One embodiment of the present invention provides a method and a system that facilitates structural coverage of a design during a design verification process. During operation, the system receives a hardware description of the design, which contains one or more modul... | 08/19/2008 |
| 7415395 | Symbolic evaluation engine for high-performance simulations A method is provided of simulating a system. The method defines equations modeling the system using terms having characteristics encapsulated within the term. Next, the method performs symbolic processing on the established equations for simplification. Additionally... | 08/19/2008 |
| 7415403 | Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure A method for simulating analog behavior of a circuit in a simulation system includes representing the circuit as a hierarchically arranged set of branches, which includes a root branch and a plurality of other branches logically organized in a graph. The hierarchica... | 08/19/2008 |
| 7412634 | On-chip sampling circuit and method Through addressing circuitry, a sampling circuit can choose a unique internal node/signal on an encapsulated/packaged chip to be output to one or more drivers. The chosen signals available at the target node are directed either through a select circuit to an output ... | 08/12/2008 |
| 7412671 | Apparatus and method for verifying an integrated circuit pattern A first generator section generates a tolerance data corresponding to a target pattern set based on a design data of a semiconductor device. A second generator section generates an image data of a semi-conductor device pattern formed based on the target pattern. An ... | 08/12/2008 |
| 7412672 | Method and apparatus for broadcasting scan patterns in a scan-based integrated circuit A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple sc... | 08/12/2008 |
| 7412676 | Integrated OPC verification tool An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification components. The integrated verification and manufacturability includes a hierarchical datab... | 08/12/2008 |
| 7412677 | Detecting reducible registers Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condi... | 08/12/2008 |
| 7412678 | Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchr... | 08/12/2008 |
| 7412673 | Integrated system noise management—bounce voltage A method for determining an allowable simultaneous switching output level on a bank-by-bank basis is described. An inductance scaling factor is determined for a first bank. A noise limit scaling factor is determined for the first bank. A bounce voltage scaling facto... | 08/12/2008 |
