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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Number | Title | Issue Date |
| 7478346 | Debugging system for gate level IC designs A synthesizer or emulator processes a gate level IC design derived from an RTL design to produce a gate level dump file indicating how signals of the gate level design behave. The gate level dump file is converted into an RTL dump file indicating how signals of the ... | 01/13/2009 |
| 7478347 | Semiconductor manufacturing apparatus, management apparatus therefor, component management apparatus therefor, and semiconductor wafer storage vessel transport apparatus A semiconductor manufacturing apparatus having a plurality of portions according to this invention includes a storage device which stores, for each portion, information representing the lapsed time of use or the product processing count till occurrence of a failure ... | 01/13/2009 |
| 7475367 | Memory power models related to access information and methods thereof A power consumption model for a memory device is provided. According to each characteristic vector, a corresponding power lookup table is built. Each characteristic vector comprises an operating mode and a variation of the data and/or address status of the memory de... | 01/06/2009 |
| 7475368 | Deflection analysis system and method for circuit design A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for ea... | 01/06/2009 |
| 7472362 | Method of minimizing phase noise A method of minimizing phase noise is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the i... | 12/30/2008 |
| 7469391 | Method and device of analyzing crosstalk effects in an electronic device For analyzing the effects of crosstalk in an electronic device, a model description of the electronic device is provided which defines a victim net and at least one aggressor net, the model description allowing for simulating the dynamic response behaviour at an out... | 12/23/2008 |
| 7467363 | Method for SRAM bitmap verification A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit “defect” is int... | 12/16/2008 |
| 7467362 | Failure detection improvement apparatus, failure detection improvement program, failure detection improvement method A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to an appropriate location on the net list; and a net list output sectio... | 12/16/2008 |
| 7464349 | Method and system or generating a current source model of a gate Aspects for generating a current source model of a gate include extracting the current source model of the gate. The current source model of the gate is a function of time and output voltage of the gate. Further, the current source model of the gate is extracted bas... | 12/09/2008 |
| 7464350 | Method of and circuit for verifying a layout of an integrated circuit device A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated circuit device; generating an implant table file having data showing a r... | 12/09/2008 |
| 7461363 | System and method for analyzing response values sum of differential signals A method for analyzing response values sum of differential signals includes: receiving configurations of simulation parameters; simulating differential signal paths with an analog transmission channel according to a design file; analyzing the analog transmission cha... | 12/02/2008 |
| RE40597 | Evaluation TEG for semiconductor device and method of evaluation An evaluation TEG for evaluating a semiconductor device including an SOI structure and a LOCOS having a birdbeak portion comprises two electrodes 10 and 20 having different electrode widths sufficiently large to disregard the length of the LOCOS birdbe... | 12/02/2008 |
| 7458044 | CDM ESD event simulation and remediation thereof in application circuits Methods and structure for improved simulation of CDM ESD events and for remediation of circuit designs correcting for previously inexplicable damage to core circuits of an application circuit design caused by such events. Features and aspects hereof note that such p... | 11/25/2008 |
| 7454723 | Validation of electrical performance of an electronic package prior to fabrication An electrical resistance determination method. Input to the method includes a description of at least one electrical network within a substrate. The description includes specification of a plurality of first ports on a first side of the substrate, and a plurality of... | 11/18/2008 |
| 7451412 | Speeding up timing analysis by reusing delays computed for isomorphic subcircuits One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist... | 11/11/2008 |
| 7448003 | Signal flow driven circuit analysis and partitioning technique A method for generating a layout for an analog circuit design is provided. The method includes tracing a signal flow through a circuit netlist, and partitioning the circuit netlist into a digital portion and an analog portion. A signal flow is defined through the an... | 11/04/2008 |
| 7448002 | Inspection system An inspection system applicable to a data processing device installed with a PCB (printed circuit board) design software and a display unit is proposed, wherein the PCB design software is used for creating PCB totems for a multi-layer PCB, the display unit is used t... | 11/04/2008 |
| 7444275 | Multi-variable polynomial modeling techniques for use in integrated circuit design Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage s... | 10/28/2008 |
| 7444574 | Stimulus extraction and sequence generation for an electric device under test A method and system that utilizes a graphical interface that enables a user to select and capture building blocks of a Device Under Test (DUT) test scenario from a previously run test case or from multiple stimulation results. Each of these extracted building block ... | 10/28/2008 |
| 7444602 | Method of generating ASIC design database When a function design has been carried out by an RTL description using an HDL language, a CPU of an integrated circuit design support apparatus writes data such as a simulation time, a layout area, a timing and a power consumption into a header portion of the RTL d... | 10/28/2008 |
| 7444604 | Apparatus and methods for simulation of electronic circuitry A system for analyzing a model of an electronic circuit, which includes at least one non-linear circuit element, includes a computer. The computer replaces the non-linear circuit element with a linearized circuit model that approximates a behavior of the non-linear ... | 10/28/2008 |
| 7444610 | Visualizing hardware cost in high level modeling systems Within a high level modeling system (HLMS), a method of visualizing a circuit design can include identifying the circuit design and reading hardware cost information for the circuit design. The method also can include presenting a graphical representation of the cir... | 10/28/2008 |
| 7441219 | Method for creating, modifying, and simulating electrical circuits over the internet The present invention enables a user to create, modify, simulate and save an electrical circuit using an Internet browser over an Internet connection. The user can change the connectivity of the circuit as well as add and/or remove components in a free form manner. ... | 10/21/2008 |
| 7441216 | Applying CNF simplification techniques for SAT-based abstraction refinement The present embodiment keeps track of a set of resolution required for generating each one of the clauses added by the simplification method. This information is used by the method that generates the unsat core in order to extract the original clauses that generated... | 10/21/2008 |
| 7441215 | Hierarchical netlist comparison by relevant circuit order The present invention uses the strength of modern hierarchical integrated circuit design to speed up the comparison of two netlists. Instead of working from bottom-up it can proceed with arbitrary hierarchical order to do the comparison. This has the advantage that ... | 10/21/2008 |
| 7441212 | State machine recognition and optimization State machines are identified from a netlist of circuit elements of a user design. Strongly connected components in the netlist are identified as candidates for analysis. The registers of each strongly connected component are identified. An optimal set of inputs and... | 10/21/2008 |
| 7441214 | Semiconductor integrated circuit designing apparatus, semiconductor integrated circuit designing method, semiconductor integrated circuit manufacturing method, and readable recording media In LSI design, gate level logic circuit information, standard cell library information, and package information of a circuit block constituting an LSI chip are inputted, noise analysis is performed for the LSI chip using the inputted information, and the processing ... | 10/21/2008 |
| 7441210 | On-the-fly RTL instructor for advanced DFT and design closure A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (... | 10/21/2008 |
| 7437280 | Hardware-based co-simulation on a PLD having an embedded processor Co-simulation of an electronic circuit design using an embedded processor on a programmable logic device (PLD). The programmable logic resources of a PLD are used to perform hardware-based co-simulation of a first portion of the electronic circuit design. Software-b... | 10/14/2008 |
| 7437692 | Memory debugger for system-on-a-chip designs A simulation/debugging method for SOC designs that utilizes initial memory values loaded into a simulation model. A test program is then executed, and incremetal transaction records are generated for each incremental memory access (e.g., data write operations). Each... | 10/14/2008 |
| 7437693 | Method and system for s-parameter generation Disclosed are methods and systems for generating S-parameters. In some embodiments, the methods and systems comprise creating (e.g., extracting, calculating, generating), in part or whole into the development environment, S-parameters of the given netlist, which may... | 10/14/2008 |
| 7437694 | System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design A system and method for identifying, for a selected signal, those signals whose value is relevantly determined based upon a value of the selected signal, where a set of signals to be examined is identified as those signals that satisfy one or more of the following c... | 10/14/2008 |
| 7437695 | Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices A method of performing timing analysis on a circuit design for an integrated circuit (IC) can include selecting a physical portion of the IC that includes at least one instance of a logic hierarchy and generating a local timing constraint specific to the physical po... | 10/14/2008 |
| 7437696 | Method and device for determining the time response of a digital circuit A method and a device determine a time response of a digital circuit. The time response is determined as a time difference between a data delay of a data path of the digital circuit, and a clock delay of a clock signal, which causes storage of a data item on the dat... | 10/14/2008 |
| 7434181 | Debugger of an electronic circuit manufactured based on a program in hardware description language A device for debugging an electronic circuit manufactured based on an initial program in hardware description language comprising an instrumentation unit capable of determining a first additional circuit capable of activating a first observation signal representativ... | 10/07/2008 |
| 7434182 | Method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip A method is provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expe... | 10/07/2008 |
| 7434183 | Method and system for validating a hierarchical simulation database System and method for validating a circuit for simulation are disclosed. The system includes at least one processing unit for executing computer programs, a graphical user interface for viewing representations of the circuit on a display, a memory for storing inform... | 10/07/2008 |
| 7434184 | Method for detecting flaws in a functional verification plan This method uses 2 copies of the design under test. These 2 copies use different values (including primary inputs and initial states) to feed the supposedly irrelevant logic while using the same (or consistent as desired) values to feed the feature being verified. S... | 10/07/2008 |
| 7434185 | Method and apparatus for parallel data preparation and processing of integrated circuit graphical design data A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of inter... | 10/07/2008 |
| 7434186 | Method and system for calculating high frequency limit capacitance and inductance for coplanar on-chip structure Capacitance and inductance expressions used for modeling critical on-chip metal interconnects. A method for calculating high frequency limit capacitances C∞ and inductances L∞ of coplanar transmission line structures over silicon substrate ... | 10/07/2008 |
