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| Number | Title | Issue Date |
| 7398503 | Method and apparatus for pre-tabulating sub-networks A method for pre-tabulating sub-networks that (1) generates a sub-network that performs a function, (2) generates a parameter based on this function, and (3) stores the sub-network based on the parameter. In some embodiments, the generated sub-network has several ci... | 07/08/2008 |
| 7395516 | Manufacturing aware design and design aware manufacturing Some embodiments of the invention provide a process for designing and manufacturing an integrated circuit (“IC”). The process selects a wiring configuration and an illumination configuration. The process uses the selected wiring configuration to design an IC lay... | 07/01/2008 |
| 7395519 | Electronic-circuit analysis program, method, and apparatus for waveform analysis A design-change-target-circuit detecting unit inputs circuit information including an element model describing an electronic circuit to detect an electronic circuit using a changed element model. A determining unit compares a characteristic of an element model befor... | 07/01/2008 |
| 7395518 | Back end of line clone test vehicle A test vehicle comprises at least one product layer having a east one product circuit pattern on the product layer, and one or more clone layers formed over the product layer (1902). The one or more clone layers include a plurality of structures, which may in... | 07/01/2008 |
| 7392169 | Method, system and program product for defining and recording minimum and maximum event counts of a simulation utilizing a high level language According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the ... | 06/24/2008 |
| 7392489 | Methods and apparatus for implementing application specific processors Methods and apparatus are provided for efficiently implementing an application specific processor. An application specific processor includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Bo... | 06/24/2008 |
| 7392490 | System and method of modelling capacitance of on-chip coplanar transmission line structures over a substrate Methods, systems and apparatus for modeling capacitance for a structure comprising a pair of long conductors surrounded by a dielectric material and supported by a substrate. In particular, the structure may be on-chip coplanar transmission lines over a conductive s... | 06/24/2008 |
| 7392168 | Method of compensating for etch effects in photolithographic processing A computer system reads data corresponding to an IC layout target layer and performs an etch simulation on the target layer. Etch biases are calculated and the inverse of the etch biases are used to produce a new target layer. The new target layer is provided as an ... | 06/24/2008 |
| 7389481 | Integrated circuit design utilizing array of functionally interchangeable dynamic logic cells A circuit arrangement, integrated circuit device, apparatus, program product, and method utilize an array of functionally interchangeable dynamic logic cells to implement an application specific logic function in an integrated circuit design. Each functionally inter... | 06/17/2008 |
| 7389490 | Method, system and program product for providing a configuration specification language supporting selective presentation of configuration entities In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With ... | 06/17/2008 |
| 7389482 | Method and apparatus for analyzing post-layout timing violations A tool for analyzing timing violations reports is presented herein. The tool comprises a script which parses a log file containing any number of timing violation reports from a simulation of a layout design. The tool filters, consolidates, and sorts the timing viola... | 06/17/2008 |
| 7389215 | Efficient presentation of functional coverage results A method for presentation of functional coverage includes representing a set of attributes of a design under test as a multi-dimensional cross-product space, which includes events corresponding to combinations of values of the attributes to be tested, the events inc... | 06/17/2008 |
| 7389480 | Content based yield prediction of VLSI designs A system, method and program product for predicting yield of a VLSI design. A method is provided including the steps of: identifying and grouping sub-circuits contained within an integrated circuit design by type; calculating critical area values for regions within ... | 06/17/2008 |
| 7386816 | Method for manufacturing an electronic device having an electronically determined physical test member A method for manufacturing an electronic device such as an integrated circuit or display device is provided. A design description of the electronic device is generated using a computer aided design tool. Physical device data representing a physical description of th... | 06/10/2008 |
| 7386815 | Test yield estimate for semiconductor products created from a library Disclosed is a method that predicts test yield for a semiconductor product, prior to design layout. This is accomplished by applying a critical area analysis to individual library elements that are used to form a specific product and by estimating the test yield imp... | 06/10/2008 |
| 7386819 | Methods of verifying functional equivalence between FPGA and structured ASIC logic cells Structured ASIC circuitry that is intended to be functionally equivalent to a programmed block of FPGA circuitry (e.g., a programmed FPGA LUT) is verified for such functional equivalence by using the specification (logical or physical) for the structured ASIC circui... | 06/10/2008 |
| 7386817 | Method of determining stopping powers of design structures with respect to a traveling particle A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a posi... | 06/10/2008 |
| 7386776 | System for testing digital components In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from... | 06/10/2008 |
| 7386820 | Method and apparatus for formally checking equivalence using equivalence relationships An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFG and HLMDFG. RTLMDFG and HLMDFG are then put into timestep form and are called RTLM | 06/10/2008 |
| 7383520 | Method and apparatus for optimizing thermal management system performance using full-chip thermal analysis of semiconductor chip designs A method and apparatus for optimizing cooling system performance using full-chip thermal analysis of semiconductor chip designs is provided. One embodiment of a novel method for optimizing the cooling of an electronic system incorporating at least one semiconductor ... | 06/03/2008 |
| 7383519 | Systems and methods for design verification using selectively enabled checkers Systems and methods for performing design verification testing in which test cases are analyzed to determine the characteristics that will be verified in a module under test, and in which the identified characteristics are used to selectively enable checker modules ... | 06/03/2008 |
| 7383521 | Characterization and reduction of variation for integrated circuits A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture o... | 06/03/2008 |
| 7383518 | Method and apparatus for performance metric compatible control of data transmission signals The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a differential signal as received by a receiver of a data transmission... | 06/03/2008 |
| 7383523 | Semiconductor integrated circuit To provide a semiconductor integrated circuit in which a clock signal supplied to each flip-flop will not be adversely affected when a functional change is made using a spare flip-flop. The semiconductor integrated circuit includes a plurality of main flip-flops whi... | 06/03/2008 |
| 7380226 | Systems, methods, and apparatus to perform logic synthesis preserving high-level specification A method and an apparatus to perform logic synthesis preserving high-level specification and to check that a common specification (CS) of two circuits is correct have been disclosed. In one embodiment, the method includes building a circuit N2 that preser... | 05/27/2008 |
| 7380225 | Method and computer program for efficient cell failure rate estimation in cell arrays A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determ... | 05/27/2008 |
| 7380227 | Automated correction of asymmetric enclosure rule violations in a design layout Automated techniques may correct certain rule violations, simplifying and automating the design layout of an electronic circuit, whether embodied as a design encoding or as a fabricated electronic circuit. Violations of enclosure design rules, those specifying the m... | 05/27/2008 |
| 7380228 | Method of associating timing violations with critical structures in an integrated circuit design A method and computer program product for associating timing violations with critical structures in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) identifying a critical structure in the integrated circuit des... | 05/27/2008 |
| 7380220 | Dummy fill for integrated circuits A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing proc... | 05/27/2008 |
| 7380224 | Method and system for non-linear state based satisfiability A computerized method and system for solving non-linear Boolean equations is disclosed comprising at least partially solving a Boolean function; developing at least one inference regarding said Boolean function and saving said inference to a state machine; and acces... | 05/27/2008 |
| 7376919 | Methods and apparatuses for automated circuit optimization and verification Methods and apparatuses to automatically determine conditions at hierarchical boundaries of a hierarchical circuit design and to use the determined conditions in hierarchical optimization and verification. In one embodiment, a hierarchical block is optimized and tra... | 05/20/2008 |
| 7376918 | Probabilistic noise analysis A method of determining whether voltage from an aggressor net exceeds a voltage threshold on a victim net design in an integrated circuit design. Probabilistic noise from the aggressor net on the victim net is calculated. The probabilistic noise is checked against t... | 05/20/2008 |
| 7376916 | Performing a constrained optimization to determine circuit parameters One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the ... | 05/20/2008 |
| 7376544 | Vector transfer during co-simulation Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling system (HLMS). A hardware-implemented block in the design is co-simul... | 05/20/2008 |
| 7376917 | Client-server semiconductor verification system A client-server semiconductor verification system is described. The system comprises a client device storing a test job having test vectors and configuration data for programmable logic for testing a design of a logic circuit. A server is coupled to the client devic... | 05/20/2008 |
| 7373624 | Method and system for performing target enlargement in the presence of constraints A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or... | 05/13/2008 |
| 7373627 | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) fo... | 05/13/2008 |
| 7373619 | Post-silicon test coverage verification In one embodiment, the invention is directed to a method of optimizing post-silicon test coverage for a system under test (“SUT”). The method comprises defining coverage data comprising Hardware Description Language (“HDL”) events; testing the SUT using a sy... | 05/13/2008 |
| 7373618 | Method and system for selection and replacement of subcircuits in equivalence checking A system, method, computer program, and article of manufacture for generating a golden circuit including datapath components for equivalence checking of synthesized revised circuit. The method includes generating a set of static, dynamic and derived candidates for t... | 05/13/2008 |
| 7373576 | Apparatus, method, and signal-bearing medium embodying a program for verifying logic circuit design A method and a signal-bearing medium embodying a program for a logic circuit design verification apparatus which includes a dynamic verification device that verifies a logic circuit executing a logic simulation, a static verification device that verifies the logic c... | 05/13/2008 |
