Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 7921383 | Photolithographic process simulation including efficient result computation for multiple process variation values A method, system, and related computer program products and computer-readable numerical arrays for computer simulation of a photolithographic process is described. In one preferred embodiment, simulation of a photolithographic process is provided in which a computat... | 04/05/2011 |
| 7904844 | System, method, and computer program product for matching cell layout of an integrated circuit design An automated system for checking an integrated circuit cell layout includes searching the cell layout for a sub-area containing a predefined identifier, determining a reference cell layout corresponding to the predefined identifier, verifying the cell layout by comp... | 03/08/2011 |
| 7904845 | Determining locations on a wafer to be reviewed during defect review Various methods, designs, defect review tools, and systems for determining locations on a wafer to be reviewed during defect review are provided. One computer-implemented method includes acquiring coordinates of defects detected by two or more inspection systems. Th... | 03/08/2011 |
| 7904843 | Systematic generation of scenarios from specification sheet A method of generating a scenario includes generating a specification model by describing a specification in a predetermined descriptive language, extracting a plurality of operations from the specification model, generating a plurality of operation descriptions, ea... | 03/08/2011 |
| 7900164 | Structure to measure both interconnect resistance and capacitance A structure for measuring both interconnect resistance and capacitance. The structure comprises a plurality of metallic interconnects, a first circuit for measuring capacitance charging current at a first interconnect and a second circuit for measuring the voltage d... | 03/01/2011 |
| 7900165 | Determining a design attribute by estimation and by calibration of estimated value A computer-implemented method of determining an attribute of a circuit includes using a computationally expensive technique to simulate the attribute (such as timing delay or slew) of a portion of the circuit, at predetermined values of various parameters (e.g. nomi... | 03/01/2011 |
| 7900166 | Method to produce an electrical model of an integrated circuit substrate and related system and article of manufacture A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective lo... | 03/01/2011 |
| 7895540 | Multilayer finite difference methods for electrical modeling of packages and printed circuit boards Disclosed are exemplary finite difference methods for electromagnetically simulating planar multilayer structures. The exemplary finite difference methods simulate multilayer planes by combining the admittance matrices of single plane pairs and equivalent circuit mo... | 02/22/2011 |
| 7895541 | Semiconductor integrated circuit pattern verification method, photomask manufacturing method, semiconductor integrated circuit device manufacturing method, and program for implementing semiconductor integrated circuit pattern verification method A semiconductor integrated circuit pattern verification method includes executing simulation to obtain a simulation pattern to be formed on a substrate on the basis of a semiconductor integrated circuit design pattern, comparing the simulation pattern and the design... | 02/22/2011 |
| 7890900 | Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum ... | 02/15/2011 |
| 7890899 | Variable clocked scan test improvements Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for s... | 02/15/2011 |
| 7890897 | Measure of analysis performed in property checking The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constrain... | 02/15/2011 |
| 7890898 | Method for semiconductor circuit Capacity-gate voltage characteristics of a field-effect transistor having plural gates are measured against a voltage change in each one of the gates for an inverted MOSFET and for an accumulated MOSFET, respectively. These measurements together with numerical simul... | 02/15/2011 |
| 7886240 | Modifying layout of IC based on function of interconnect and related circuit and design structure Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the la... | 02/08/2011 |
| 7886241 | System and method for automated electronic device design A system for the automated formation and control and execution of an electronic device design flow is disclosed which can enable more efficient electronic device design methodology with higher quality of results. Such a system as analysis methods, techniques, and to... | 02/08/2011 |
| 7882464 | Method and system for power distribution analysis Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with t... | 02/01/2011 |
| 7882467 | Test pattern evaluation method and test pattern evaluation device Provided are an evaluation method and device of a test pattern which enable an appropriate evaluation in a reliability test with a simulation time reduced and high accuracy. It is assumed that each possible internal state of a cell determined at least by a logic val... | 02/01/2011 |
| 7882465 | FPGA and method and system for configuring and debugging a FPGA The present invention provides a Field Programmable Gate Array (FPGA), a system for debugging a Field Programmable Gate Array, a method for debugging a Field Programmable Gate Array, a FPGA configuration data product and a method and system for configuring a FPGA. A... | 02/01/2011 |
| 7882466 | Noise checking method and apparatus, and computer-readable recording medium in which noise checking program is stored There is provided a technique in which internal wires of a large cell are spuriously patterned and treated as object of a noise check. Internal wires of a large cell are spuriously determined based on terminal information and wiring forbidden information of the larg... | 02/01/2011 |
| 7877710 | Method and apparatus for deriving signal activities for power analysis and optimization A method for managing vectorless estimation includes identifying a semantic structure. A signal activity is assigned to an output of the semantic structure. Vectorless estimation is performed on non-semantic structures. ... | 01/25/2011 |
| 7877715 | Method and apparatus to use physical design information to detect IR drop prone test patterns A method is provided to evaluate whether one or more test patterns is power safe for use during manufacturing testing of an integrated circuit that includes a nonuniform power grid and that includes a scan chain, the method comprising: assigning respective toggle co... | 01/25/2011 |
| 7877713 | Method and apparatus for substrate noise analysis using substrate tile model and tile grid A method is provided to evaluate substrate noise propagation in an integrated circuit design, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instance... | 01/25/2011 |
| 7877716 | Computer program products for determining stopping powers of design structures with respect to a traveling particle A computer program product, comprising a computer readable storage device having a computer readable program code stored therein, said program code including an algorithm adapted to be executed by a computer to implement a method. First, design information of a desi... | 01/25/2011 |
| 7877711 | Methods of deriving switch networks A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch netwo... | 01/25/2011 |
| 7877712 | System for and method of verifying IC authenticity A verification system disclosed herein uses the unique signatures of an IC to perform authentication of the IC after the IC is shipped to a customer. The verification system records the fingerprint and associated IC identifier with the fingerprint into a data struct... | 01/25/2011 |
| 7877714 | System and method to optimize semiconductor power by integration of physical design timing and product performance measurements A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscill... | 01/25/2011 |
| 7873925 | Method and apparatus for computing test margins for at-speed testing In one embodiment, the invention is a method and apparatus for computing margins for at-speed testing of integrated circuit chips. One embodiment of a method for computing a margin for at-speed testing of an integrated circuit chip design includes computing a statis... | 01/18/2011 |
| 7870521 | Method of designing an electronic device and device thereof A plurality of sequential nodes in a design file for an electronic device are identified and an effective switching capacitance is determined for a first sequential node of the plurality of sequential nodes based upon statically predicted operation of a first device... | 01/11/2011 |
| 7870520 | Semiconductor device and yield calculation method A semiconductor device yield calculation method and a computer program that include selecting from a designed device pattern a specified first pattern and a second pattern that differs from the first pattern, finding a probability that the second pattern passes a te... | 01/11/2011 |
| 7870517 | Method and mechanism for implementing extraction for an integrated circuit design An improved method and system for performing extraction on an integrated circuit design is disclosed. Extraction can be performed at granularities much smaller than the entire IC design, in which a halo is used to identify a geometric volume surrounding an object of... | 01/11/2011 |
| 7870518 | Predictive event scheduling in an iterative resolution network A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is... | 01/11/2011 |
| 7870522 | Efficient communication of data between blocks in a high level modeling system A method communicates data with efficient conversion between representations in a high-level modeling system. The data is communicated from a first block in a first external format and the data is communicated to a second block in a second external format. The first... | 01/11/2011 |
| 7870519 | Method for determining features associated with fails of integrated circuits A method for testing an integrated circuit and analyzing test data. The method includes: defining a set of signal path selection criteria; selecting a subset of signal paths of an integrated circuit design, the selecting signal paths meeting the selection criteria; ... | 01/11/2011 |
| 7865850 | Method and apparatus for substrate noise aware floor planning for integrated circuit design A methodology is provided to perform noise analysis in the implementation stage of the design of an integrated circuit, and based upon analysis results, a floorplan may be adjusted or guard rings may be inserted to reduce the impact of digital switching noise upon n... | 01/04/2011 |
| 7865849 | System and method for estimating test escapes in integrated circuits A method for designing an integrated circuit including estimating a test escape rate for tests of interest, a test coverage calculator and a system for estimating a test escape rate for tests of interest associated with a portion of an integrated circuit (IC) die. I... | 01/04/2011 |
| 7861194 | Method and apparatus for calculating wiring capacitance, and computer product A diagonal-capacitance calculating unit calculates diagonal capacitance based on the adjacent wirings in diagonally upward and downward direction from a target wiring. A basic-capacitance correcting unit corrects basic capacitance, which is wiring capacitance based ... | 12/28/2010 |
| 7861196 | System and method for multi-exposure pattern decomposition Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analys... | 12/28/2010 |
| 7861195 | Process for design of semiconductor circuits The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, a... | 12/28/2010 |
| 7856607 | System and method for generating at-speed structural tests to improve process and environmental parameter space coverage A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic... | 12/21/2010 |
| 7856608 | Method and apparatus for generating current source noise model for creating semiconductor device model used in power supply noise analysis A model generation method for generating a semiconductor device model used for power supply noise analysis, is performed by, calculating noise values for various circuit elements based on current source noise waveforms calculated in accordance with a current flowing... | 12/21/2010 |
