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A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 6195790 | Electrical parameter evaluation system, electrical parameter evaluation method, and computer-readable recording medium for recording electrical parameter evaluation program A ƊZ calculator calculates difference between an inversion layer capacitance by a classical theory and an inversion layer capacitance by a quantum theory, calculates ƊZ which is a thickness of a semiconductor substrate equivalent to the difference in in... | 02/27/2001 |
| 6195789 | Method for circuit design on a spherical semiconductor having critical dimensions A method for designing a circuit on a spherical shaped semiconductor device using a great circle and a small, which is either parallel or perpendicular to the great circle, to define critical dimensions needed for the circuit. A great-circle-small-circle ... | 02/27/2001 |
| 6187483 | Mask quality measurements by fourier space analysis A method (200) of determining an optimal mask fabrication process includes fabricating (202) a first mask pattern (220) on a mask using a first mask fabrication process and a second mask pattern (222) on a mask using a second mask fabrication process, whe... | 02/13/2001 |
| 6183916 | Method for proximity effect compensation on alternative phase-shift masks with bias and optical proximity correction A method of forming an alternative phase shifting mask and forming a circuit pattern on a wafer using the mask are described. Optical proximity correction is added to a data file, in which a description of a circuit pattern has been stored, to obtain a fi... | 02/06/2001 |
| 6178544 | Simulation mesh generation method, apparatus, and program product A method, computer system, and a computer readable medium is disclosed for generating triangular meshes for the purpose of performing high-speed generation of triangular meshes with boundary protection layers. One use for the invention is in simulations s... | 01/23/2001 |
| 6154717 | Computer simulation method of impurity with pileup phenomenon A simulation method is provided, which makes it possible to simulate diffusion of doped impurity in Si and SiO2 in consideration of the pileup phenomenon of the doped impurity without using any intermediate layer. In the step (a), a mesh having... | 11/28/2000 |
| 6144929 | Method of simulating impact ionization phenomenon in semiconductor device A method of simulating an impact ionization phenomenon of a semiconductor device, by which an electric characteristic concerning the impact ionization phenomenon of the semiconductor device is obtained by setting a mesh in a space and by solving a Poisson... | 11/07/2000 |
| 6080200 | Diffusion simulation method for impurities using mesh points and branches utilizing concentrations of electrically active impurities and effective impurity electric field mobility A total impurity concentration which is a result of the solution of a diffusion equation at the immediately preceding point of time is used to solve, for each mesh point, an equation for determining an electrically active impurity concentration to approxi... | 06/27/2000 |
| 6064810 | System and method for predicting the behavior of a component A system (2) predicts the behavior of a component using refinements in both space and time. The system (2) includes a steady-state engine (14) that generates a steady-state stencil (16) that defines successively refined meshes (58, 60, 90, 118, 122) in sp... | 05/16/2000 |
| 6052517 | Spherical cell design for VLSI circuit design on a spherical semiconductor A method for designing a circuit on a spherical shaped semiconductor integrated circuit using uniform unit shapes capable of cover the surface of the sphere in a matingly corresponding orientation with adjacent unit shapes. The method includes the steps o... | 04/18/2000 |
| 6047116 | Method for generating exposure data for lithographic apparatus In a method of generating from design data the exposure data necessary for a multistage-deflection charged beam exposure device that has a main deflector and a sub-deflector and forms a pattern, before a shape larger than the size of a minimum subfield ar... | 04/04/2000 |
| 5946479 | Method and device for generating mesh for use in numerical analysis A method and device for generating mesh to be used in numerical analysis for regions of an object to be analyzed, the regions of an object to be analyzed being input as data for a geometric model which defines their geometric form in a coordinate system w... | 08/31/1999 |
| 5933359 | Method, apparatus and computer program product for simulating ion implantation An ion-implantation simulation method including (1) a step of generating orthogonal meshes for a multilayer-structure substrate, (2) a step of taking out a longitudinal strip, (3) a step of determining a function representing an impurity distribution in t... | 08/03/1999 |
| 5920487 | Two dimensional lithographic proximity correction using DRC shape functions Integrated circuit designs are continually shrinking in size. Lithographic processes are used to transfer these designs to a semiconductor substrate. These processes typically require that the exposure wavelength of light be shorter than the smallest dime... | 07/06/1999 |
| 5889678 | Topography simulation method In a topography simulation method, the topography of a resist pattern after curing treatment can be precisely estimated without producing a complex physical model or performing parameter measurement. Specifically, in the method of estimating the topograph... | 03/30/1999 |
| 5889686 | Profile simulation method A profile of a developed resist is exactly simulated irrespective of whether or not a resist pattern is dense. A dissolution rate of a film to be processed, which film is provided on a substrate, is varied in accordance with a concentration of a developer... | 03/30/1999 |
| 5880977 | Mesh generation device and its method for generating meshes having a boundary protective layer A mesh generation device comprising a boundary protective layer generating unit, a mesh point positioning unit, a triangular mesh generation unit and a triangular mesh checking unit, characterized in that the triangular mesh generating unit generates tria... | 03/09/1999 |
| 5838594 | Method and apparatus for generating finite element meshes, and analyzing method and apparatus A finite element mesh generating method generates triangular meshes used in finite element method analysis. This finite element mesh generating method includes the steps of (a) inputting orthogonal meshes used in finite difference method and mesh joining ... | 11/17/1998 |
| 5828586 | High speed device simulating method In a method for simulating parameters including a potential in a semiconductor device, deviations of the parameters are calculated for a plurality of nodes of a mesh in the semiconductor device by Newton's method. However, when absolute values of electric... | 10/27/1998 |
| 5819073 | Simulation method and simulator A simulation method and a simulator determine a profile of particles, by determining whether or not each reaction formula, which describes a reaction of particles to generate reactants in semiconductor solids or gases, is in equilibrium, determining unkno... | 10/06/1998 |
| 5812412 | Charged beam pattern data generating method and a charged beam pattern data generating apparatus A charged beam pattern data generating method for generating high quality pattern data from the circuit layout design data of a semiconductor device for use by a charged beam drawing apparatus in the production of resist patterns or other semiconductor de... | 09/22/1998 |
| 5808892 | Line edge and size definition in e-beam exposure An e-beam processing method for improving micron and submicron line quality and resolution by selecting one of several recipes each containing recursive expressions for evaluating figure pattern fracturing and e-beam processing parameters based on the siz... | 09/15/1998 |
| 5774696 | Triangle and tetrahedron mesh generation method A method for eliminating intersections between a substance boundary and triangles (or tetrahedra) of a triangle mesh (or tetrahedron mesh) which satisfies a condition of Delaunay partition and is used for a finite difference method. First, triangles inter... | 06/30/1998 |
| 5768156 | Connectivity-based, all-hexahedral mesh generation method and apparatus The present invention is a computer-based method and apparatus for constructing all-hexahedral finite element meshes for finite element analysis. The present invention begins with a three-dimensional geometry and an all-quadrilateral surface mesh, then co... | 06/16/1998 |
| 5745388 | Profile simulation method and pattern design method A profile simulation method of predicting a profile of a surface of a film to be processed which changes when the surface of the film on a substrate is physically or chemically processed, is characterized by comprising the steps of setting a plurality of ... | 04/28/1998 |
| 5710711 | Method and integrated circuit adapted for partial scan testability A method and apparatus are taught which modify digital integrated circuits for partial scan testing and do so with little or no impact on the circuit's performance characteristics. Illustratively, the scan memory elements are selected from among all memor... | 01/20/1998 |
| 5699271 | Method of automatically generating program for solving simultaneous partial differential equations by use of finite element method A program generating method for generating a FORTRAN program by use of a computer having the following steps of automatically selecting an optimal weight function for each equation of the system of partial differential equations including coupled plural v... | 12/16/1997 |
| 5687355 | Apparatus and method for modeling a graded channel transistor The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel porti... | 11/11/1997 |
| 5684723 | Device simulation method and device simulator A simulation method for obtaining internal information at discrete points within a semiconductor device to be analyzed based on information related to the semiconductor device by forming a coefficient matrix A having matrix equation A.multidot.X=b with re... | 11/04/1997 |
| 5677846 | Device simulator and mesh generating method thereof A device simulator including a boundary protection layer generation portion for generating a boundary protection layer which will not cause parasitic resistance in the vicinity of a boundary between different components of a semiconductor device whose ele... | 10/14/1997 |
| 5675521 | Multichip module analyzer The disclosure describes a method for performing thermal reliability analysis of electronic devices such as multichip modules. The method supports the reliabilty of multichip technology during the design phase by integrating traditional thermal analysis t... | 10/07/1997 |
| 5675522 | Method and system for dividing analyzing region in device simulator In order to divide an analyzing region in a semiconductor device into a plurality of fractional elements of a predetermined configuration, the analyzing region is initially divided into an arbitrary number of the fractional elements. With respect to a new... | 10/07/1997 |
| 5671167 | Method and apparatus for forming a model for use in finite element method analysis A method forms an analyzing model for use in finite element method analysis. The method includes the steps of (a) detecting faces of elements of the analyzing model which do not make contact with faces of other elements, based on information related to th... | 09/23/1997 |
| 5671395 | Method and system for dividing analyzing region in device simulator A region of a semiconductor device to be analyzed is initially divided a plurality of fractional elements of predetermined configuration. With respect to each fractional element, adjacent element information is provided. Then, a new nodal point is added. ... | 09/23/1997 |
| 5648920 | Method and apparatus for deriving total lateral diffusion in metal oxide semiconductor transistors A method and apparatus for deriving total lateral diffusion in MOS transistors includes deriving (40) a DC model. The DC model is then verified (42) with a multifinger transistor. The gate of the multifinger transistor is then isolated (44). Voltage pulse... | 07/15/1997 |
| 5646870 | Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers A method and system are disclosed for: (a) matching a machine-implemented process simulator with an actual fabrication line, (b) using the matched model to simulate the statistical results of mass production by the modeled production line, (c) using the m... | 07/08/1997 |
| 5644688 | Boolean trajectory solid surface movement method A method for simulating changes to the topography of a workpiece, e.g. a semiconductor wafer, as it undergoes process steps. The method may be used to simulated isotropic or anisotropic deposition or etch process steps. A solids modeling system is used to... | 07/01/1997 |
| 5617322 | Mesh generator and generating method A mesh generator includes a mesh generation processing unit for setting a two-dimensional triangular mesh satisfying the conditions of the Delaunay partitioning on a semiconductor device to be analyzed, a triangular element deletion unit for deleting a pr... | 04/01/1997 |
| 5553009 | Parallel method for subdivision of arbitrary curved solids A method and system are provided for subdividing an arbitrarily shaped object into a collection of geometric elements ("cells") having predefined, simple topologies which facilitate further subdivision into tetrahedra, and which are well suited for furthe... | 09/03/1996 |
| 5481475 | Method of semiconductor device representation for fast and inexpensive simulations of semiconductor device manufacturing processes A data structure is used in semiconductor process integration studies for manufacture of device structures, where one dimension of the data structure is used to represent each film layer in the device and one or two additional dimensions represent vertica... | 01/02/1996 |
