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| Number | Title | Issue Date |
| 7934173 | Reverse dummy insertion algorithm A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different type... | 04/26/2011 |
| 7934172 | SLM lithography: printing to below K1=.30 without previous OPC processing Previously disclosed methods and devices are extended in this application by two-dimensional analysis of optical proximity interactions and by fashioning a computationally efficient kernel for rapid calculation of adjustments to be made. The computations can be made... | 04/26/2011 |
| 7926000 | Integrated circuit system employing dipole multiple exposure An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist ... | 04/12/2011 |
| 7900169 | OPC model calibration process A method of calibrating a model of a lithographic process includes a plurality of test features each having different widths that vary from a resolvable feature width that is known to be resolvable by the lithographic process, to a width that is known not to be reso... | 03/01/2011 |
| 7895547 | Test pattern based process model calibration Embodiments of the present invention provide a method for performing lumped-process model calibration. The method includes creating a plurality of sub-process models for a set of sub-processes; creating a lumped-process-model incorporating said set of sub-processes;... | 02/22/2011 |
| 7882480 | System and method for model-based sub-resolution assist feature generation Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would impr... | 02/01/2011 |
| 7873935 | Method of manufacturing a mask A method of manufacturing a mask includes designing a first mask data pattern, designing a second mask data pattern for forming the first mask data pattern, acquiring a first emulation pattern, which is predicted from the second mask data pattern, using layout-based... | 01/18/2011 |
| 7873936 | Method for quantifying the manufactoring complexity of electrical designs A method and system for quantifying manufacturing complexity of electrical designs randomly places simulated defects on image data representing electrical wiring design. The number of distinct features in the image data without the simulated defects and the number o... | 01/18/2011 |
| 7870531 | System for using partitioned masks to build a chip A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard int... | 01/11/2011 |
| 7865863 | OPC conflict identification and edge priority system An integrated circuit verification system provides an indication of conflicts between an OPC suggested correction and a manufacturing rule. The indication specifies which edge segments are in conflict so that a user may remove the conflict to achieve a better OPC re... | 01/04/2011 |
| 7861207 | Fragmentation point and simulation site adjustment for resolution enhancement techniques A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial si... | 12/28/2010 |
| 7861209 | Method for interlayer and yield based optical proximity correction An optical proximity correction method is provided using a modified merit function based upon yield. Known failure mechanisms related to layout geometries are used to derive yield functions based upon distance values between layout features, such as, edge features. ... | 12/28/2010 |
| 7861208 | Structure for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks A design structure, method, and system for partitioned dummy fill shapes for reduced mask bias with alternating phase shift masks, or with other two-mask lithographic processes employing a trim mask. A design structure is embodied in a machine readable medium used i... | 12/28/2010 |
| 7853919 | Modeling mask corner rounding effects using multiple mask layers An embodiment provides systems and techniques for determining an improved process model which models mask corner rounding (MCR) effects. During operation, the system may receive a mask layout and process data which was generated by applying a photolithography proces... | 12/14/2010 |
| 7853918 | Reverse dummy insertion algorithm A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different type... | 12/14/2010 |
| 7849436 | Method of forming dummy pattern A method of forming a dummy pattern on a mask for fabricating a semiconductor device is disclosed. The method may include a step of calculating a distance in a device isolation area between a first chip area and a second chip area having different pattern densities.... | 12/07/2010 |
| 7844938 | Data correcting hierarchical integrated circuit layout accommodating compensate for long range critical dimension variation A solution for performing a data correction on a hierarchical integrated circuit layout is provided. A method includes: receiving a CD compensation map for the long range critical dimension variation prior to the data correction; grouping compensation amounts of the... | 11/30/2010 |
| 7840932 | Defocus determination method using sub-resolution feature (SRF) printing The present application is directed to apparatus and methods for determining a magnitude of defocus and a direction of defocus for a photolithography process. A sub-resolution feature on a reticle which is not printed on a wafer at the best focus offset, but is form... | 11/23/2010 |
| 7831953 | Lithography simulation method, program and semiconductor device manufacturing method A lithography simulation method which predicts the result that a pattern formed on a mask is transferred onto a sample by use of a simulation based on pattern data of the mask includes subjecting a mask layout containing a pattern whose periodicity is disturbed to t... | 11/09/2010 |
| 7827520 | Method for correcting optical proximity effect A method of correcting an optical proximity effect may include the steps of: fabricating a test mask having test patterns; projecting patterns on a wafer using the test mask; measuring line widths of the patterns formed on the wafer; and executing a model calibratio... | 11/02/2010 |
| 7827518 | Incrementally resolved phase-shift conflicts in layouts for phase-shifted features Phase shifting allows generating very narrow features in a printed features layer. Thus, forming a fabrication layout for a physical design layout having critical features typically includes providing a layout for shifters. Specifically, pairs of shifters can be pla... | 11/02/2010 |
| 7827519 | Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielect... | 11/02/2010 |
| 7823118 | Computer readable medium having multiple instructions stored in a computer readable device A computer readable medium comprising multiple instructions stored in a computer readable device, upon executing these instructions, a computer performing the following steps: providing a semiconductor layout and a circuit pattern; setting a forbidden area of the ci... | 10/26/2010 |
| 7818708 | Method and system for developing post-layout electronic data automation (EDA) applications A method and system for processing geometrical layout design data to manufacture an electronic circuit is provided. The method includes extracting the geometrical layout design data from one or more data-format files. The method further includes segregating the geom... | 10/19/2010 |
| 7818707 | Fast pattern matching Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying featur... | 10/19/2010 |
| 7814456 | Method and system for topography-aware reticle enhancement The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planariz... | 10/12/2010 |
| 7810065 | System and method for implementing optimized creation of openings for de-gassing in an electronic package System and method for designing an electronic package. A placement manager receives a physical design of an electronic package from a packaging design tool. The placement manager receives design constraints regarding the physical design for the electronic package. T... | 10/05/2010 |
| 7805699 | Shape-based photolithographic model calibration A method and apparatus for determining how well a photolithographic model simulates a photolithographic printing process. A test pattern of features is printed on a wafer and the shape of the printed features is compared with the shape of simulated features produced... | 09/28/2010 |
| 7802225 | Optical proximity correction method, optical proximity correction apparatus, and optical proximity correction program, method of manufacturing semiconductor device, design rule formulating method, and optical proximity correction condition calculating method In the present invention, there is provided an optical proximity correction method including steps of: extracting a gate length distribution of a gate from a pattern shape of the gate of a transistor to be formed on a wafer; calculating electric characteristics of t... | 09/21/2010 |
| 7802224 | Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium A semiconductor device has first wiring layers 30 and a plurality of dummy wiring layers 32 that are provided on the same level as the first wiring layers 30. The semiconductor device defines a row direction, and first virtual linear lines L1... | 09/21/2010 |
| 7793253 | Mask-patterns including intentional breaks A method for determining a mask pattern to be used on a photo-mask in a photolithographic process is described. During the method, a target pattern that includes at least one continuous feature is provided. Then a mask pattern that includes a plurality of distinct t... | 09/07/2010 |
| 7793254 | Method and system for designing a timing closure of an integrated circuit Aspects for designing a timing closure of an integrated circuit include instantiating a minimum repeater between at least one block and a corresponding blockage if an interconnect crosses the corresponding blockage and according to a drive of the blockage. The aspec... | 09/07/2010 |
| 7788628 | Computational efficiency in photolithographic process simulation Photolithographic process simulation is described in which fast computation of resultant intensity for a large number of process variations and/or target depths (var,zt) is achieved by computation of a set of partial intensity functions independent of (va... | 08/31/2010 |
| 7788626 | Pattern data correction method, pattern checking method, pattern check program, photo mask producing method, and semiconductor device manufacturing method A pattern data correction method is disclosed, which comprises preparing an integrated circuit pattern, setting a tolerance to the pattern that is allowable error range when the pattern is transferred on a substrate, creating a target pattern within the tolerance, a... | 08/31/2010 |
| 7788627 | Lithography verification using guard bands A method for verifying a lithographic process is described. During the method, a set of guard bands are defined around a target pattern that is to be printed on a semiconductor die using a photo-mask in the lithographic process. An estimated pattern is calculated us... | 08/31/2010 |
| 7784018 | Method and apparatus for identifying a manufacturing problem area in a layout using a gradient-magnitude of a process-sensitivity model One embodiment of the present invention provides a system that identifies an area in a mask layout which is likely to cause manufacturing problems. During operation, the system creates an on-target process model that models a semiconductor manufacturing process unde... | 08/24/2010 |
| 7784015 | Method for generating a mask layout and constructing an integrated circuit Methods are disclosed for the layout and manufacture of microelectronic circuits. The methods employ the monitoring of the placement of macros within circuit layouts for design rule compliance. Upon detection of noncompliance, the macros associated with noncomplianc... | 08/24/2010 |
| 7784016 | Method and system for context-specific mask writing A method for generating lithography masks includes generating integrated circuit design data and using context information from the integrated circuit design data to write a mask. ... | 08/24/2010 |
| 7784019 | Yield based retargeting for semiconductor design flow A method for modifying an integrated circuit design layout is presented and can include placing a plurality of target points in the proximity of a polygon representing a portion of the integrated circuit design; modifying the target point placement for some or all o... | 08/24/2010 |
| 7784017 | Lithography simulation method, photomask manufacturing method, semiconductor device manufacturing method, and recording medium A lithography simulation method includes obtaining a mask transmission function from a mask layout, obtaining an optical image of the mask layout by using the mask transmission function, obtaining a function which is filtered by applying a predetermined function fil... | 08/24/2010 |
