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| Number | Title | Issue Date |
| 7904850 | System and method for converting software to a register transfer (RTL) design A method for converting a C-type programming language program to a hardware design, where the said program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synth... | 03/08/2011 |
| 7900168 | Customizable synthesis of tunable parameters for code generation An apparatus, method and/or computer readable media automatically generate hardware description language (HDL) code. A design environment is configured to receive a hardware design, the hardware design including a plurality of numerical parameters. A user interface ... | 03/01/2011 |
| 7895546 | Statistical design closure A method of statistical design closure is disclosed. The method generally includes the steps of (A) reading statistical data from a database, the statistical data defining a plurality of chip yield improvements, one of the chip yield improvements in each one of a pl... | 02/22/2011 |
| 7890911 | Skeleton generation apparatus and method A skeleton generation method includes: creating a netlist which is a circuit connection information input file format for analog circuit simulation, as subcircuit descriptions corresponding to function blocks of a system, on the basis of input and output information... | 02/15/2011 |
| 7886252 | Same subgraph detector for data flow graph, high-order combiner, same subgraph detecting method for data flow graph, same subgraph detection control program for data flow graph, and readable recording medium A same sub-graph detection apparatus for data flow graph is disclosed. An embodiment of the present invention detects a sub-graph at a high speed, in which an area-size reduction effect is large. The same sub-graph detection apparatus for data flow graph according t... | 02/08/2011 |
| 7886253 | Design structure for performing iterative synthesis of an integrated circuit design to attain power closure A design structure that performs iterative synthesis of an integrated circuit design to attain power closure is described. In one embodiment, the design structure is embodied in a computer readable medium and has the capability to initially synthesized an integrated... | 02/08/2011 |
| 7882479 | Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory A method and apparatus implement redundant memory access using multiple controllers on the same bank of memory, and a design structure on which the subject circuit resides is provided. A first memory controller uses the memory as its primary address space, for stora... | 02/01/2011 |
| 7865862 | Design structure for dynamically selecting compiled instructions A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first executi... | 01/04/2011 |
| 7853917 | System for building binary decision diagrams efficiently in a structural network representation of a digital circuit A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is... | 12/14/2010 |
| 7844937 | Method and apparatus for making a semiconductor device using hardware description having merged functional and test logic blocks A processor-implemented method for making a semiconductor device having a test logic block and a functional logic block is provided. The method includes retrieving hardware description for at least one test logic block and mapping the hardware description for the at... | 11/30/2010 |
| 7840931 | Loop manipulation if a behavioral synthesis tool Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset... | 11/23/2010 |
| 7831952 | Designing apparatus, designing method, and program An apparatus, method, and program for designing a semiconductor device having a storage unit configured to a differential signal library for use in generation of a design data of a differential signal cell that receives or outputs differential signals. The apparatus... | 11/09/2010 |
| 7831951 | Task concurrency management design method A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionali... | 11/09/2010 |
| 7827517 | Automated register definition, builder and integration framework A system for designing an integrated circuit is provided. The system includes a plurality of class databases having register information extracted from a register entry tool. A system integration tool is used to integrate the register information from each of the cl... | 11/02/2010 |
| 7823116 | Hierarchical analog layout synthesis and optimization for integrated circuits In embodiment of the invention, a method of synthesizing a layout of an integrated circuit chip including analog circuitry is disclosed. The method includes receiving a circuit netlist of an integrated circuit chip including analog circuitry; representing and manipu... | 10/26/2010 |
| 7823117 | Separating a high-level programming language program into hardware and software components Various approaches are described for implementing a high-level programming language program in hardware and software components. In one approach, a method comprises compiling the high-level programming language program into a target language program that includes a ... | 10/26/2010 |
| 7814455 | Logic synthesis method and device The present invention provides a logic synthesis method and the like that can shorten the execution time and the confirmation time required for logic re-synthesis and logic equivalence checking. The logic synthesis method characteristically includes the steps of: ex... | 10/12/2010 |
| 7805698 | Methods and systems for physical hierarchy configuration engine and graphical editor In one embodiment a new method to address configuring a logical design and libraries of design elements with additional information is proposed that may be used to create a physical design from that logical design. Logical designs may be generic, while physical desi... | 09/28/2010 |
| 7802223 | Method and system for configurable contacts for implementing different bias designs of an integrated circuit device In a computer implemented synthesis system, a fabrication method for an integrated circuit device. The method includes receiving a circuit netlist representing a first form of an integrated circuit design to be realized in physical form. A plurality of contacts of t... | 09/21/2010 |
| 7793252 | Mask pattern preparation method, semiconductor device manufacturing method and recording medium A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent ima... | 09/07/2010 |
| 7788625 | Method and apparatus for precharacterizing systems for use in system level design of integrated circuits Systems, methods, software, and techniques can be used to precharacterize a variety of prototype system designs. The prototype system designs can be defined at one or more levels of abstraction. The prototype designs are characterized using one or more electronic de... | 08/31/2010 |
| 7784014 | Generation of a specification of a network packet processor A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation... | 08/24/2010 |
| 7784013 | Method for the definition of a library of application-domain-specific logic cells The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention p... | 08/24/2010 |
| 7774735 | Integrated circuit netlist migration A method for migrating a netlist from one set of library cells to a new set of library cells with minimal time and effort and without loss of information within an ASCI environment. This methodology ensures that during translation logic equivalence and scan configur... | 08/10/2010 |
| 7765514 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of ... | 07/27/2010 |
| 7765513 | Configuration database supporting selective presentation of configuration entities In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With ... | 07/27/2010 |
| 7752593 | Method for improved synthesis of binary decision diagrams with inverted edges and quantifiable as well as nonquantifiable variables A method, system and computer program product for performing synthesis of representations is disclosed. The method comprises receiving a representation of a relation and building a gate representing an OR function of one or more selected parent paths into a node of ... | 07/06/2010 |
| 7735049 | Mask network design for scan-based integrated circuits A method and apparatus for selectively masking off unknown (‘x’) captured scan data in first selected scan cells 220 from propagating through the scan chains 221 for test, debug, diagnosis, and yield improvement of a scan-based integrated circuit | 06/08/2010 |
| 7735048 | Achieving fast parasitic closure in a radio frequency integrated circuit synthesis flow Methods achieve fast parasitic closure in IC (integrated circuit) synthesis flow with particular application to RFIC (radio frequency integrated circuit) synthesis flow. Parasitic corners generated based on earlier layout statistics are incorporated into circuit res... | 06/08/2010 |
| 7735051 | Method for replicating and synchronizing a plurality of physical instances with a logical master Design Data Management uses one copy of common data sets along with a plurality of instances, while continuing to utilize the existing design databases and existing CAD tools. Allowing a minimum amount of user intervention to create and maintain the common data set,... | 06/08/2010 |
| 7716625 | Logic circuit and method of logic circuit design A complementary logic circuit contains a first logic input, a second logic input, a first dedicated logic terminal, a second dedicated logic terminal, a first logic block, and a second logic block. The first logic block consists of a network of p-type transistors fo... | 05/11/2010 |
| 7716624 | Mask creation with hierarchy management using cover cells A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical fil... | 05/11/2010 |
| 7694266 | Method and apparatus for dynamic frequency voltage switching circuit synthesis Methods and apparatus provide for automated synthesis of an integrated circuit whose voltage is varied during operation (also known as dynamic voltage and frequency scaling or DVFS). The automation may include estimating technology parameters from timing libraries, ... | 04/06/2010 |
| 7689965 | Generation of an extracted timing model file A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing cha... | 03/30/2010 |
| 7685555 | Macro inference within electronic design automation tools using hardware description language templates Within an Electronic Design Automation (EDA) tool, a method of macro inference can include translating a hardware description language (HDL) template into a macro template and translating a circuit design into a format corresponding to the macro template. The method... | 03/23/2010 |
| 7673275 | Development system for an integrated circuit having standardized hardware objects Embodiments of the invention include a system for integrated circuit development. Elements of the development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement d... | 03/02/2010 |
| 7673276 | Method and system for conducting a low-power design exploration Method and system for conducting low-power design explorations are disclosed. The method includes receiving an RTL netlist of a circuit design, creating one or more power requirement files, wherein each power requirement file comprises power commands corresponding t... | 03/02/2010 |
| 7669166 | Generation of a specification of a processor of network packets A method for generating a hardware description language (HDL) specification of a processor of network packets. Independent sets of interdependent handlers are determined from a specification of the handlers for processing the network packets. Either a first pipeline... | 02/23/2010 |
| 7669165 | Method and system for equivalence checking of a low power design Method and system for equivalence checking of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of a circuit, receiving a power specification file for describing power requirements of the circuit, ... | 02/23/2010 |
| 7665059 | System and method for designing multiple clock domain circuits A Hardware Description Language (HDL) utilizing a Term Rewriting System (TRS) is provided that simplifies handling of clocks, and signaling between various clock domains of a multi-clock domain circuit specification. A specific clock data type is supplied for use wi... | 02/16/2010 |
