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| Number | Title | Issue Date |
| 7194719 | Basic cell, edge cell, wiring shape, wiring method, and shield wiring structure A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides... | 03/20/2007 |
| 7191380 | Defect-tolerant and fault-tolerant circuit interconnections Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the... | 03/13/2007 |
| 7191113 | Method and system for short-circuit current modeling in CMOS integrated circuits A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair with... | 03/13/2007 |
| 7191427 | Method for mapping a logic circuit to a programmable look up table (LUT) The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being ac... | 03/13/2007 |
| 7191426 | Method and apparatus for performing incremental compilation on field programmable gate arrays A method for designing a system on a target device utilizing field programmable gate arrays (FPGAs) includes generating a first design for the system that includes a first netlist describing a first logical design, and placement and routing of the first logical desi... | 03/13/2007 |
| 7191416 | System and method for modifying integrated circuit hold times A method of arranging an integrated circuit to correct for hold time errors comprises fixing the position of existing cells in a design, determining hold time errors required to be corrected and placing buffer cells in spaces in the existing design. By placing buffe... | 03/13/2007 |
| 7188322 | Circuit layout methodology using a shape processing application A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology an... | 03/06/2007 |
| 7188063 | Capturing test/emulation and enabling real-time debugging using an FPGA for in-circuit emulation A method for obtaining real-time debug information, e.g., state information and trace information, from an FPGA acting as a virtual microcontroller that is attached to a microcontroller under test. The two devices, the microcontroller and the FPGA execute the same i... | 03/06/2007 |
| 7187663 | Flexible processing system A multi-mode wireless device on a single substrate includes an analog portion and a digital portion integrated on the single substrate. The analog portion includes a cellular radio core; and a short-range wireless transceiver core. The digital portion includes a mul... | 03/06/2007 |
| 7188043 | Boundary scan analysis A circuit testing approach involves the generation of boundary scan information using test vectors to identify characteristics of a circuit design and a boundary scan implementation therefor. According to an example embodiment of the present invention, test vectors ... | 03/06/2007 |
| 7188219 | Buffer control system and method for a memory system having outstanding read and write request buffers A memory controller and method for managing the issuance of read and write requests to a system memory is provided. The number of outstanding read requests and write requests issued to the system memory are separately monitored and further issuance of read and write... | 03/06/2007 |
| 7184801 | Mobile application builder A method and system which allow a user to define and edit workflow applications for a mobile device, screens associated with the applications, and workflow process is described. The states or schemas for these applications may be stored as records in databases. ... | 02/27/2007 |
| 7185162 | Method and apparatus for programming a flash memory A method and apparatus for programming nonvolatile (flash) memory in a microcontroller. A nonvolatile memory in the microcontroller is connected via data, address and control signal paths to a processor internal to the microcontroller. These paths are not available ... | 02/27/2007 |
| 7185309 | Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in r... | 02/27/2007 |
| 7185293 | Universal hardware device and method and tools for use therewith A universal hardware device including at least one plurality of cells for storing data; and at least one programmable matrix coupled to the at least one plurality of cells, whereby a plurality of hardware applications may be implemented by selectively storing data i... | 02/27/2007 |
| 7185294 | Standard cell library having globally scalable transistor channel length A standard cell library having a globally scalable transistor channel length is provided. In this library, the channel length of every transistor within a cell can be globally scaled, within a predetermined range, without changing cell functionality, cell size, or c... | 02/27/2007 |
| 7185307 | Method of fabricating and integrated circuit through utilizing metal layers to program randomly positioned basic units A method of fabricating an integrated circuit. The integrated circuit has a semiconductor body. The method includes forming a plurality of basic units with the same component characteristic on the semiconductor body, and forming at least a layout layer to program th... | 02/27/2007 |
| 7181718 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create speciali... | 02/20/2007 |
| 7181584 | Dynamic command and/or address mirroring system and method for memory modules A memory module includes a memory hub that couples signals to memory devices mounted on opposite first and second surfaces of a memory module substrate. The memory devices are mounted in mirrored configuration with mirrored terminals of memory devices on opposite su... | 02/20/2007 |
| 7181704 | Method and system for designing integrated circuits using implementation directives A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing... | 02/20/2007 |
| 7180522 | Apparatus and method for distributed memory control in a graphics processing system A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memor... | 02/20/2007 |
| 7181359 | Method and system of generic implementation of sharing test pins with I/O cells The present invention provides a method and a system of generic implementation of sharing test pins with I/O cells. The method includes a step of making a general change in a testlib file. The testlib file is suitable for controlling I/O cell pins to gain test acces... | 02/20/2007 |
| 7178122 | Semiconductor integrated circuit, method of designing semiconductor integrated circuit, and device for designing the same Placement is performed by using a library created by enlarging cell frames of at least one type of cells out of a plurality of types of standard cells constituted by using transistors having different characteristics for the respective types of cell. More preferably... | 02/13/2007 |
| 7178123 | Schematic diagram generation and display system A system for processing a netlist description of a circuit to generate a display of a schematic diagram including representations of cells and nets first determines positions of the cell instance representations within the schematic diagram and then displays the sch... | 02/13/2007 |
| 7177182 | Rewriteable electronic fuses Rewriteable electronic fuses include latches and/or logic gates coupled to one or more nonvolatile memory elements. The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predet... | 02/13/2007 |
| 7174477 | ROM redundancy in ROM embedded DRAM Redundancy in a read only memory (ROM) embedded dynamic random access memory (DRAM) is accomplished by programming redundancy elements such as antifuses or registers with ROM data which is read instead of erroneous data. Multiple identical arrays of ROM bits can als... | 02/06/2007 |
| 7174409 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 02/06/2007 |
| 7174519 | Vector Logic techniques for multilevel minimization Very complex (multilevel) logical expressions are represented in a vector format. The logic is simplified by identifying opposing couples (a literal and its negation) and replacing symmetrical logic expressions attached to the opposing couples with a single version.... | 02/06/2007 |
| 7171633 | Estimating quality during early synthesis A computer aided system includes a method of improving the accuracy, optimization, and minimization for the synthesis and mapping of logical functions into the logical structures of a target technology, such as the logic cells (e.g., look-up tables) of a programmabl... | 01/30/2007 |
| 7171644 | Implementation set-based guide engine and method of implementing a circuit design A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing direc... | 01/30/2007 |
| 7170121 | Computer system architecture using a proximity I/O switch One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive ... | 01/30/2007 |
| 7170315 | Programmable system on a chip A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architectur... | 01/30/2007 |
| 7167922 | Method and apparatus for providing automatic ingress filtering Disclosed is a method for routing data packets, as is a data packet router (10) that operates in accordance with the invention. The method includes establishing an ingress filter (20) in individual ones of a plurality of line cards (14) installe... | 01/23/2007 |
| 7167908 | Facilitating operation of a multi-processor system via a resolved symbolic constant According to some embodiments, operation of a multi-processor system is facilitated via a resolved symbolic constant. For example, configuration information may be determined at a management processor of a multi-processor network router adapted to receive and transm... | 01/23/2007 |
| 7167025 | Non-sequentially configurable IC Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a... | 01/23/2007 |
| 7168052 | Yield driven memory placement system A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the des... | 01/23/2007 |
| 7164491 | Identifying apparatus, apparatus to be identified, identifying method, and printing apparatus An encoder of a process unit encodes an identification code output by the CPU of a main unit, thereby obtaining a response code. The response code is returned to the main unit. The logic of the encoder is changeable. At shipment, a first logic is set in the encoder.... | 01/16/2007 |
| 7165229 | Generating optimized and secure IP cores Methods and apparatus are provided for securely generating IP cores. A designer selects and configures parameterizable IP cores provided for implementation on a programmable chip. The IP cores are processed using mechanisms such as scripts to parameterize and custom... | 01/16/2007 |
| 7165230 | Switch methodology for mask-programmable logic devices A mask-programmable logic device that implements a pre-existing circuit design and that includes programmable smart switches is provided. The smart switches are metal terminals that may be programmed to perform configuration-related logic functions of the pre-existi... | 01/16/2007 |
| 7162410 | In-circuit emulator with gatekeeper for watchdog timer A watchdog timer control using a gatekeeper in an In-Circuit Emulation system. The In-Circuit Emulation system has a microcontroller operating in lock-step synchronization with a virtual microcontroller. When a watchdog event occurs, the gatekeeper, forming a part o... | 01/09/2007 |
