Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 7890910 | Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device ... | 02/15/2011 |
| 7886251 | System and method for building configurable designs with hardware description and verification languages An invention is provided for building configurable designs synthesizable to gates. The invention includes creating a configurable design using an HDL. The configurable design has a plurality of instantiated configurable constructs that can be optionally included in ... | 02/08/2011 |
| 7827516 | Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to ... | 11/02/2010 |
| 7802222 | Generalized constraint collection management method Techniques are provided to allow users of Electronic Design Automation (EDA) tools to define constraint template types for efficiently associating constraints with design objects to specify design intent. Processes for creating and validating the constraints are pro... | 09/21/2010 |
| 7797666 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Wher... | 09/14/2010 |
| 7797667 | Hardware acceleration of functional factoring A hardware accelerator factors functions during the compilation of a user design. The hardware accelerator includes cofactor units, each adapted to determine a cofactor of a function in response to a specified factorization and a set of input values. The factorizati... | 09/14/2010 |
| 7784012 | System and method for creating a standard cell library for use in circuit designs A standard cell library including a first set of cells including mixed threshold voltage cells. Each mixed threshold voltage cell includes a first threshold voltage device having a first threshold voltage and a second threshold voltage device having a second thresho... | 08/24/2010 |
| 7779381 | Test generation for low power circuits In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power... | 08/17/2010 |
| 7757199 | Logic description library of differential input circuit To present a logic description library of differential input circuit capable of expressing logically, in a differential input circuit, by including an input and output response characteristic depending on the voltage level of individual differential input signals in... | 07/13/2010 |
| 7757200 | Structure of an apparatus for programming an electronically programmable semiconductor fuse A design structure for an apparatus for programming an electronically programmable semiconductor fuse. The apparatus applies a programming current to a fuse link as a series of multiple pulses. Application of the programming current as a series of multiple short pul... | 07/13/2010 |
| 7752592 | Scheduler design to optimize system performance using configurable acceleration engines A reusable hardware control structure is provided for a hardware acceleration engine that can be configured for implementation within an electronic integrated circuit design according to any one of a plurality of configuration alternatives. The reusable hardware con... | 07/06/2010 |
| 7735047 | Method for technology mapping considering boolean flexibility Disclosed are processor-implemented methods for technology mapping a logic network onto programmable logic resources of a programmable logic device. The methods include determining respective Boolean flexibility values for a plurality of functionally equivalent mapp... | 06/08/2010 |
| 7735046 | E-fuse and method An e-fuse circuit, a method of programming the e-fuse circuit, and a design structure of the e-fuse circuit. The method includes in changing the threshold voltage of one selected field effect transistor of two field effect transistors connected to different storage ... | 06/08/2010 |
| 7725871 | SAT-based technology mapping framework Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configur... | 05/25/2010 |
| 7725870 | Method for radiation tolerance by implant well notching A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act... | 05/25/2010 |
| 7725869 | Method and apparatus for modeling multiple instances of an electronic circuit using an imperative programming language description Method and apparatus for modeling multiple instances of an electronic circuit using an imperative programming language description is described. In one example, a program is defined using an imperative programming language. The program includes multiple calls to a f... | 05/25/2010 |
| 7698681 | Method for radiation tolerance by logic book folding A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions... | 04/13/2010 |
| 7685554 | Determination of data rate and data type in a high-level electronic design Determining data rates and data types in a an electronic design. In one embodiment, an electronic design is created in a memory arrangement in response to user input. The electronic design includes a plurality of functional blocks and a plurality of nets connecting ... | 03/23/2010 |
| 7676784 | Methods and apparatus for implementing parameterizable processors and peripherals Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic... | 03/09/2010 |
| 7669164 | Hardware and software implementation of an electronic design in a programmable logic device Implementing an electronic design having software-implemented blocks and hardware-implemented blocks. A specification of the electronic design is created in response to selection of blocks from a library, and at least one of the blocks is available for implementatio... | 02/23/2010 |
| 7669163 | Partial configuration of a programmable gate array using a bus macro and coupling the third design A method of partially reconfiguring a field programmable gate array (FPGA) with at least one design that has interdesign routing with at least one other design programmed into the FPGA. A first configuration data set implements a first design in a first area of the ... | 02/23/2010 |
| 7640528 | Hardware acceleration of functional factoring A hardware accelerator factors functions during the compilation of a user design. The hardware accelerator includes cofactor units, each adapted to determine a cofactor of a function in response to a specified factorization and a set of input values. The factorizati... | 12/29/2009 |
| 7631285 | Support method for designing a semiconductor device In a support method of designing a semiconductor device, a plurality of wiring lines are arranged in parallel in a wiring line layer to transfer a same signal. A wiring line inhibition area is set in the wiring line layer to cover a space between the plurality of wi... | 12/08/2009 |
| 7617472 | Regional signal-distribution network for an integrated circuit Signal distribution of a regional signal is described. An integrated circuit includes a global signal distribution network, a regional signal distribution network and a regional buffer. The regional buffer has an output coupled at an end of the regional signal distr... | 11/10/2009 |
| 7617471 | Processor event interface for programmable integrated circuit based circuit designs A method of implementing a circuit design on a programmable integrated circuit can include displaying a list of at least one memory of the circuit design that is associated with the processor. A plurality of attributes of an event for the processor can be received. ... | 11/10/2009 |
| 7596775 | Method for determining a standard cell for IC design IC design flow includes RTL design, synthesis, APR, and layout. An IC designer can choose a suitable standard cell for an integrated circuit according to the timing, area, and BCI (best cell index) of each standard cell. Further, the BCI of a standard cell can be ge... | 09/29/2009 |
| 7596774 | Hard macro with configurable side input/output terminals, for a subsystem A hard macro device (HMD), for a subsystem (TMi) such as a data processor, comprises a processing core (C) provided with at least one time critical input terminal (CIT) adapted to feed it with time critical input data to be processed and at least one time critical o... | 09/29/2009 |
| 7587699 | Automated system for designing and developing field programmable gate arrays An automated system and method for programming field programmable gate arrays (FPGAS) is disclosed for implementing user-defined algorithms specified in a high level language. The system is particularly suited for use with image processing algorithms and can speed u... | 09/08/2009 |
| 7571415 | Layout of power device A layout of a power device is provided. The layout includes a substrate, a unit array, a plurality of first, second, third and fourth signal paths, and a first, second, third and fourth port. The unit array with a plurality of rows is disposed on the substrate. Each... | 08/04/2009 |
| 7571414 | Multi-project system-on-chip and its method A multi-project system-on-chip bench by integrating multiple system-on-chip projects into a chip, which uses a system chip bench, therefore, microprocessor, bus, embedded memory, peripheral component and input/output port is used together by those system-on-chip pro... | 08/04/2009 |
| 7549139 | Tuning programmable logic devices for low-power design implementation A method of operating a programmable logic device includes the steps of using a full VDD supply voltage to operate a first set of active blocks of the programmable logic device, and using a reduced supply voltage (e.g., 0.9 VDD) to operate a se... | 06/16/2009 |
| 7500213 | Array-based architecture for molecular electronics An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the a... | 03/03/2009 |
| 7500214 | System and method for reducing design cycle time for designing input/output cells I. A method and system is disclosed for generating a desired input/output (I/O) cell based on a basic cell from a library. After identifying a configuration requirement for a desired I/O cell to be used for an integrated circuit design, at least one basic cell is se... | 03/03/2009 |
| 7478359 | Formation of columnar application specific circuitry using a columnar programmable logic device A columnar programmable logic device (PLD) design converted to a columnar application specific integrated circuit-like (ASIC-like) design is described. A user design is instantiated in a PLD having a columnar architecture associated with the columnar PLD design. The... | 01/13/2009 |
| 7478358 | Semiconductor integrated circuit device LSI device 100 is provided with standard cell regions 10, a plurality of standard cells 20, memory blocks 11 and a plurality of memory cells 21. Standard cells 20 are equal in height “Hs” and disposed in standard cell re... | 01/13/2009 |
| 7472370 | Comparing graphical and netlist connections of a programmable logic device A processor-implemented method is provided for comparing connections in a graphical representation of a programmable logic device (PLD) design to connections in a netlist that describes the PLD design. The netlist and an identification of each tile are input. For ea... | 12/30/2008 |
| 7464360 | Common interface framework for developing field programmable device based applications independent of a target circuit board A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD). According to one embodiment, a field programmable device (FPD) compri... | 12/09/2008 |
| 7461366 | Usage of a buildcode to specify layout characteristics A method for laying out custom integrated circuits includes the steps of preliminarily laying out a custom integrated circuit using a plurality of libraried standardized programmed cells (p-cells). Buildcode representations are then assigned for each of a plurality ... | 12/02/2008 |
| 7444613 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories Systems and methods are provided for mapping logic functions from logic elements (“LEs”) into synchronous embedded memory blocks (“EMBs”) of programmable logic devices (“PLDs”). This technique increases the amount of logic that can fit into the PLD. Wher... | 10/28/2008 |
| 7444605 | Generating a base curve database to reduce storage cost An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set id... | 10/28/2008 |
