Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 7272542 | Method and system for re-targeting integrated circuits The present invention allows a designer to easily re-target the design optimized for the device of one integrated circuit vendor to the device of another vendor. The designer can start with a set of post-routed boolean equations optimized for a certain target integr... | 09/18/2007 |
| 7272546 | Apparatus and methods for importing hardware design and generating circuit interfaces A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of th... | 09/18/2007 |
| 7272814 | Reconfiguring a RAM to a ROM using layers of metallization The present invention is a method for reconfiguring a RAM into a ROM. First a RAM is fabricated on a platform ASIC in which the memory is patterned with first and second metal layers that intersect over each cell, wherein the first metal layer comprises local core c... | 09/18/2007 |
| 7269803 | System and method for mapping logical components to physical locations in an integrated circuit design environment A system and method for mapping Intellectual Property (IP) components onto a pre-fabricated chip slice allows a user to select a target location for placement of an IP component onto a slice. A slice definition of the pre-fabricated chip slice is searched for a lega... | 09/11/2007 |
| 7269814 | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logi... | 09/11/2007 |
| 7266117 | System architecture for very fast ethernet blade The system of the present invention provides data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. The system comprises a media access control (MAC) interface to facilitate receipt ... | 09/04/2007 |
| 7266725 | Method for debugging reconfigurable architectures A method for efficiently debugging a program defining a plurality of configurations to be successively processed on a dynamically reconfigurable architecture including a plurality of logic elements cooperating with each other. The method includes storing data in a m... | 09/04/2007 |
| 7265580 | Semiconductor-integrated circuit utilizing magnetoresistive effect elements A semiconductor integrated circuit device has a plurality of circuit elements, a plurality of connection elements each of which becomes a conductive state or a nonconductive state, interconnects for supplying control signals for placing the connection elements in th... | 09/04/2007 |
| 7266786 | Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems A method and apparatus of a configurable address mapping and protection architecture and hardware for on-chip systems have been described. ... | 09/04/2007 |
| 7263478 | System and method for design verification An extractor extracts descriptions unexecuted in the logic simulation according to code coverage information for the circuit description. An examiner examines whether or not there is a possibility of executing the extracted unexecuted descriptions. A prohibited-inpu... | 08/28/2007 |
| 7263456 | On circuit finalization of configuration data in a reconfigurable circuit Reconfigurable circuits with configuration data loaders are described herein. The configuration data loaders are adapted to enable on circuit finalization of configuration data provided in symbolic form, not fully resolved. ... | 08/28/2007 |
| 7263602 | Programmable pipeline fabric utilizing partially global configuration buses A method of associating virtual stripes to physical stripes in a pipelined or ring structure comprises associating a first set of virtual stripes with at least two physical stripes and associating a second set of virtual stripes, disjoint from the first set, with at... | 08/28/2007 |
| 7260807 | Method and apparatus for designing an integrated circuit using a mask-programmable fabric One embodiment of the invention provides a system that facilitates designing an integrated circuit using a mask-programmable fabric, which contains both mask-programmable logic and a mask-programmable interconnect. During operation, the system receives a description... | 08/21/2007 |
| 7260816 | Method, system, and product for proxy-based method translations for multiple different firmware versions The present invention is a method and system for translating method calls to version-specified method calls. An interface to an underlying object is provided. Applications communicating with the underlying object use the interface. The interface is separate from the... | 08/21/2007 |
| 7257654 | PCI bridge device configured for using JTAG scan for writing internal control registers and outputting debug state An integrated device (e.g., an integrated PCI bridge device), having configuration registers for storing configuration values, device logic for generating internal state values based on the configuration values, and a JTAG interface configured for receiving a serial... | 08/14/2007 |
| 7256610 | Programmable system on a chip for temperature monitoring and control A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip ch... | 08/14/2007 |
| 7257780 | Software-to-hardware compiler A hardware-to-software compiler is provided that runs an optimization on a circuit implemented in programmable logic. The optimization allows portions of the program implemented by the circuit to be executed via software. A communication interface between the hardwa... | 08/14/2007 |
| 7257799 | Flexible design for memory use in integrated circuits A method for designing and using a partially manufactured semiconductor product is disclosed. The partially manufactured semiconductor product, referred to as a slice, contains a fabric of configurable transistors and at least an area of embedded memory. The method ... | 08/14/2007 |
| 7257795 | Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints Methods and apparatuses are disclosed to facilitate routing between a first and second component in a programmable logic device to generate a path with an appropriate amount of delay to satisfy short-path timing constraints efficiently and effectively. ... | 08/14/2007 |
| 7257800 | Method and apparatus for performing logic replication in field programmable gate arrays A method for designing a system on a target device utilizing field programmable gate arrays is disclosed. A design is synthesized for the system. Components in the design are mapped onto resources on the target device. Placement locations are determined for the comp... | 08/14/2007 |
| 7257803 | Method for constructing an integrated circuit device having fixed and programmable logic portions and programmable logic architecture for use therewith Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware d... | 08/14/2007 |
| 7253999 | On-chip latch-up protection circuit An on-chip latch-up protection circuit. The lath-up protection circuit includes a core circuit, a power switch, and a current extractor. The power switch controls major current flowing through the core circuit. The current extractor detects amplitude of the major cu... | 08/07/2007 |
| 7254800 | Methods of providing error correction in configuration bitstreams for programmable logic devices Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code i... | 08/07/2007 |
| 7254801 | Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis A system and method improves the effectiveness of logic duplication optimizations by dynamically allocating the usage of logic duplicates. Duplicate atoms in the user design are identified. Atoms satisfying heuristics can also be duplicated and added to the user des... | 08/07/2007 |
| 7253657 | Apparatus and methods for configuration of programmable logic devices A programmable logic device (PLD) includes configuration circuitry. The configuration circuitry is adapted to receive serial configuration data from a configuration device. The configuration circuitry is further adapted to program a function of the PLD without using... | 08/07/2007 |
| 7251803 | Memory re-implementation for field programmable gate arrays Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are... | 07/31/2007 |
| 7251804 | Structures and methods of overcoming localized defects in programmable integrated circuits by routing during the programming thereof Methods of programming an integrated circuit (IC) such as a programmable logic device to avoid localized defects present in the IC, and ICs capable of performing these methods. As part of an automated programming process, programmable resources utilized by a user de... | 07/31/2007 |
| 7251805 | ASICs having more features than generally usable at one time and methods of use More ASIC functionality is crammed into a chip (or chip set) than can probably or definitely be operative at one time when the chip is packaged and inserted into a broader circuit. The excessive ASIC functionality is chosen to cope with different market development ... | 07/31/2007 |
| 7248070 | Method and system for using boundary scan in a programmable logic device A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to ge... | 07/24/2007 |
| 7249010 | Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA Methods of estimating the susceptibility to single event upsets (SEUs) of a design implemented in an FPGA. In an FPGA, many of the configuration memory cells could change state in response to an SEU without affecting the functionality of a design implemented in the ... | 07/24/2007 |
| 7249329 | Technology mapping techniques for incomplete lookup tables Technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT) are provided. For example, the output of a function is compared to the output of an incomplete LUT for each binary value of the function's inpu... | 07/24/2007 |
| 7249351 | System and method for preparing software for execution in a dynamically configurable hardware environment A system and method for creating run time executables in a configurable processing element array is disclosed. This system and method includes the step of partitioning a processing element array into a number of defined sets of hardware accelerators, which in one em... | 07/24/2007 |
| 7249339 | Method and apparatus for optimizing delay paths through field programmable gate arrays A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input. ... | 07/24/2007 |
| 7249335 | Methods of routing programmable logic devices to minimize programming time Methods of routing a design in a programmable logic device (PLD) to increase the effectiveness of applying a multi-frame write (MFW) compression technique to the resulting configuration bitstream. The methods apply placement patterns and/or routing templates to enco... | 07/24/2007 |
| 7246285 | Method of automatic fault isolation in a programmable logic device The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic por... | 07/17/2007 |
| 7246339 | Methods for creating and expanding libraries of structured ASIC logic and other functions Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that eit... | 07/17/2007 |
| 7243330 | Method and apparatus for providing self-implementing hardware-software libraries Method and apparatus for providing self-implementing hardware-software libraries is described. One aspect of the invention relates to designing an embedded system for an integrated circuit. A hardware platform is defined. A software platform is defined having a plur... | 07/10/2007 |
| 7243329 | Application-specific integrated circuit equivalents of programmable logic and associated methods Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA lo... | 07/10/2007 |
| 7243175 | I/O and memory bus system for DFPs and units with two-or multi-dimensional programmable cell architectures A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can ... | 07/10/2007 |
| 7243312 | Method and apparatus for power optimization during an integrated circuit design process Method and apparatus for designing an integrated circuit is described. In an example, the integrated circuit is designed in accordance with timing constraint data. Any logic paths in the plurality of logic paths that have a timing characteristic within a threshold a... | 07/10/2007 |
