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Apparatus for Simulating a High Five
A self-righting hand-arm configuration which is adapted to pivot when struck by a user, thereby simulating a "high five."
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| Number | Title | Issue Date |
| 7490311 | Reset manager A reconfigurable module in a programmable logic device (“PLD”), such as a field-programmable gate array (“FPGA”), is reset after reconfiguration by an internal reset signal. The internal reset signal allows other modules in the PLD to remain active while the... | 02/10/2009 |
| 7490312 | Partition-based incremental implementation flow for use with a programmable logic device A method of incremental flow for a programmable logic device can include identifying elements of a hardware description language representation of a circuit design and specifying a hierarchy of partitions for selected ones of the elements. Portions of implementation... | 02/10/2009 |
| 7478357 | Versatile bus interface macro for dynamically reconfigurable designs Method and apparatus for module design in a PLD is described. In one example, a PLD includes a reconfigurable module, a static module, and at least one logic interface macro. The reconfigurable module includes a signal interface and is configured for active partial ... | 01/13/2009 |
| 7478356 | Timing driven logic block configuration A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is... | 01/13/2009 |
| 7472369 | Embedding identification information on programmable devices Methods and apparatus are provided for embedding identification information on a programmable chip. Parameterizable components are selected for implementation on a programmable chip. Information relating to the parameterizable components is embedded on the programma... | 12/30/2008 |
| 7461365 | Increased effective flip-flop density in a structured ASIC An H-tree is formed in a conducting layer over a base array of a structured ASIC, an H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of the base array and H-tree. The endpoints of the H-tree are formed at or near sequential... | 12/02/2008 |
| 7454737 | Method, system and program product for specifying and using register entities to configure a simulated or physical digital system In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possib... | 11/18/2008 |
| 7451422 | Simultaneous assignment of select I/O objects and clock I/O objects to banks using integer linear programming A method of assigning I/O objects to banks of a target device can include concurrently assigning I/O objects, including select I/O objects and clock I/O objects, of the circuit design to I/O groups according to an I/O standard associated with each I/O object. Each I... | 11/11/2008 |
| 7451423 | Determining indices of configuration memory cell modules of a programmable logic device A processor-implemented method is provided for determining first and second indices of cell instances of a configuration memory cell of a tile module of a programmable logic device (PLD) design. A netlist is input that describes the PLD design and includes the cell ... | 11/11/2008 |
| 7451421 | Methods of implementing and modeling interconnect lines at optional boundaries in multi-product programmable IC dies A method of modeling two IC dies using the same software model, although the two dies include physical differences. A first programmable logic device (PLD) die includes first and second portions, and is encoded to render the first portion operational and the second ... | 11/11/2008 |
| 7451424 | Determining programmable connections through a switchbox of a programmable logic device A processor-implemented method is provided for determining programmable connections through a switchbox module of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of the switchbox module are input. Characterizat... | 11/11/2008 |
| 7451425 | Determining controlling pins for a tile module of a programmable logic device A processor-implemented method is provided for determining controlling pins of a programmable logic device (PLD) design. A netlist that describes the PLD design and an identification of a tile module are input. Characterization data is input for a sub-module of the ... | 11/11/2008 |
| 7444601 | Trusted computing platform In a computing platform, a trusted hardware device (24) is added to the motherboard (20). The trusted hardware device (24) is configured to acquire an integrity metric, for example a hash of the BIOS memory (29), of the computing platform... | 10/28/2008 |
| 7443846 | Implementation of a multiplexer in integrated circuitry A smaller, faster implementation of a multiplexer is provided. Using an improved selection encoding, the multiplexer is implemented using LUTs that may be coupled to one another using a cascade connection structure. The improved selection encoding and cascade struct... | 10/28/2008 |
| 7441223 | Method and apparatus for performing synthesis to improve density on field programmable gate arrays A method for designing a system on a programmable logic device (PLD) includes implementing a first network of logic elements (LEs) and a second network of LEs with a combined network of LEs that performs a same functionality but utilizes a fewer number of LEs. ... | 10/21/2008 |
| 7441212 | State machine recognition and optimization State machines are identified from a netlist of circuit elements of a user design. Strongly connected components in the netlist are identified as candidates for analysis. The registers of each strongly connected component are identified. An optimal set of inputs and... | 10/21/2008 |
| 7441224 | Streaming kernel selection for reconfigurable processor In one embodiment, a subset of a set of streaming kernels of an application is selected for implementation on a reconfigurable processor. The streaming kernels are selected by first forming a stream flow graph of the application by parsing a program of instructions ... | 10/21/2008 |
| 7437486 | Configurable measurement interface coupled to a front-end subsystem and a back-end subsystem for receiving a set of bootstrap information A measurement device having a configurable measurement interface that enables the dynamic allocation of responsibilities among front-end and back-end subsystems of a measurement device. A measurement device according to the present teachings includes a front-end sub... | 10/14/2008 |
| 7434193 | Method, system and program product for specifying a configuration for a digital system utilizing dial biasing weights In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of d... | 10/07/2008 |
| 7434182 | Method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip A method is provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expe... | 10/07/2008 |
| 7433813 | Embedding a co-simulated hardware object in an event-driven simulator Various approaches for embedding a hardware object in an event-driven simulator are disclosed. The various approaches involve generating an HDL proxy component having an HDL definition of each port of the hardware object and respective event handler functions associ... | 10/07/2008 |
| 7434191 | Router Configuration of a reconfigurable multidimensional field may include prioritizing required connections between cells, establishing connections having a high priority first, and establishing additional connections after the high priority connections have been establi... | 10/07/2008 |
| 7434192 | Techniques for optimizing design of a hard intellectual property block for data transmission Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes su... | 10/07/2008 |
| 7428674 | Monitoring the state vector of a test access port Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitor... | 09/23/2008 |
| 7428721 | Operational cycle assignment in a configurable IC Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. F... | 09/23/2008 |
| 7428718 | Enhanced incremental placement during physical synthesis A method of placing a circuit design for a target device can include identifying a critical region having at least one input block and at least one output block and determining a line starting at the input block and extending to the output block. Blocks of the criti... | 09/23/2008 |
| 7426665 | Tileable field-programmable gate array architecture A method for testing FPGA routing circuitry having a plurality of first sets of tracks having programmably connectable individual track segments includes providing a global control signal to simultaneously turn on all of the programmable elements in at least two of ... | 09/16/2008 |
| 7426708 | ASICs having programmable bypass of design faults A relatively small amount of programmable or reprogrammable logic (pro-Logic) is included in a mostly-ASIC device so that such re/programmable logic can be used as a substitute for, or for bypassing a fault-infected ASIC block (if any) either permanently or at times... | 09/16/2008 |
| 7426709 | Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bu... | 09/16/2008 |
| 7426461 | Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective pluralit... | 09/16/2008 |
| 7426705 | Combined hardware/software assertion checking Assertion checking is achieved by modifying a given set of assertions to include subsuming assertions that cover one or more of given assertions and also require less logic to implement, by implementing at least the subsuming assertions in functionally reconfigurabl... | 09/16/2008 |
| 7424697 | Assigning inputs of look-up tables to improve a design implementation in a programmable logic device Methods for improving an implementation of a design in a programmable logic device (PLD). A topological level of the design implementation is determined for each look-up table (LUT) of the PLD. A subset of the LUTs that are on the critical timing paths of the design... | 09/09/2008 |
| 7424698 | Allocation of combined or separate data and control planes A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication. ... | 09/09/2008 |
| 7424696 | Power mesh for multiple frequency operation of semiconductor products The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher fr... | 09/09/2008 |
| 7421524 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s... | 09/02/2008 |
| 7418686 | System for representing the logical and physical information of an integrated circuit A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested pblocks. Each pblock ... | 08/26/2008 |
| 7418690 | Local searching techniques for technology mapping Local searches are provided for improving technology mapping for programmable logic integrated circuits. A local search algorithm is applied to a solution for mapping logic gates in a netlist to lookup tables (LUTs) on a programmable logic IC. The local search algor... | 08/26/2008 |
| 7415689 | Automatic configuration of a microprocessor influenced by an input program An automatic process for configuring a microprocessor architecture that consists of a number of execution units with configurable connectivity between them. The data and control flows within an input program are used to influence the process so that the resulting mi... | 08/19/2008 |
| 7415690 | Apparatus and methods for multi-gate silicon-on-insulator transistors An integrated circuit (IC) includes mechanisms for adjusting or setting the gate bias of one gate of one or more multi-gate transistors. The IC includes a gate bias generator. The gate bias generator is configured to set gate bias of one gate of the one or more mult... | 08/19/2008 |
| 7415681 | Optimal mapping of LUT based FPGA A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent ... | 08/19/2008 |
