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| Number | Title | Issue Date |
| 7216319 | Regional clock skew measurement technique In an embodiment of the present invention, an integrated circuit (“IC”), such as a field-programmable gate array (“FPGA”) or a complex programmable logic device (“CPLD”), has a global clock buffer coupled to a first regional clock buffer through a first ... | 05/08/2007 |
| 7215140 | Programmable logic device having regions of non-repairable circuitry within an array of repairable circuitry and associated configuration hardware and method An embodiment of the present invention provides a programmable logic device (“PLD”) including one or more dedicated blocks of circuitry within one or more repairable logic array regions. Aspects of the present invention provide circuitry and methods for controll... | 05/08/2007 |
| 7216330 | Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices by registering a user specified procedure A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locat... | 05/08/2007 |
| 7216207 | System and method for fast, secure removal of objects from disk storage A system, program storage device, and method of optimizing data placement on a storage device, the method comprising establishing a specified time constraint for which the storage device is to delete data stored thereon; dividing a data object into a plurality of da... | 05/08/2007 |
| 7216308 | Method and apparatus for solving an optimization problem in an integrated circuit layout Some embodiments of the invention provide a method of solving an optimization problem. The problem includes a plurality of elements, and one or more solutions have been previously identified for each element. The method specifies a first solution set that has one id... | 05/08/2007 |
| 7216323 | Process for designing base platforms for IC design to permit resource recovery and flexible macro placement, base platform for ICs, and process of creating ICs Base platforms customizable into ICs are designed by identifying a plurality of macros for placement on the platform, each macro being defined in part by a plurality of elements that perform respective functions of the macro. Identical elements in a plurality of mac... | 05/08/2007 |
| 7216328 | Method and system for integrating cores in FPGA-based system-on-chip (SoC) The invention provides an interface that can facilitate integration of user specific proprietary cores and commercially available cores during customization of an FPGA-based SoC. A selected hardware or software system component used for customizing the FPGA-based So... | 05/08/2007 |
| 7213224 | Customizable development and demonstration platform for structured ASICs The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible e... | 05/01/2007 |
| 7212030 | Field programmable gate array long line routing network A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of ... | 05/01/2007 |
| 7213090 | Data transfer apparatus for serial data transfer in system LSI A data transfer apparatus comprises a plurality of selectors each having two inputs and an output, and a transfer gate gating the transfer of data, wherein one inputs of the plurality of selectors are connected to respective bits of a data bus in the order that tran... | 05/01/2007 |
| 7213091 | SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connect... | 05/01/2007 |
| 7212813 | Telecommunication device with software components The present invention provides a telecommunication system that has a processing unit; a memory; and at least a software component implemented on a processing unit and using said memory. Each software component includes a set of attributes, each attribute being a poi... | 05/01/2007 |
| 7212961 | Interface for rapid prototyping system A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at le... | 05/01/2007 |
| 7210115 | Methods for optimizing programmable logic device performance by reducing congestion Methods and apparatus for designing and producing programmable logic devices are provided. A logic design system may be used to analyze various implementations of a desired logic design for a programmable logic device integrated circuit. The logic design system may ... | 04/24/2007 |
| 7205589 | Semiconductor devices fabricated with different processing options A semiconductor device that provides identical functionality and timing characteristics, fabricated with two fabricating options comprised of: a user configurable high cost fabricating option utilizing a set of masking patterns and a process sequence; and a mask pro... | 04/17/2007 |
| 7207020 | Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool A method for designing a system includes generating minimum and maximum delay budgets for connections from long-path and short-path timing constraints. The system is designed in response to the minimum and maximum delay budgets. ... | 04/17/2007 |
| 7207025 | Sea-of-cells array of transistors The invention concerns integrated circuits in which a MACRO is embedded in a standard cell array. One level of metal is devoted exclusively to non-local interconnect, and a layer of polysilicon is devoted to local interconnect, thereby saving significant space. ... | 04/17/2007 |
| 7205785 | Apparatus and method for repairing logic blocks An apparatus is described comprising: a set of logic blocks configured to perform designated data processing functions; a set of redundant logic blocks also configured to perform the designated data processing functions; and a logic block selector module to replace ... | 04/17/2007 |
| 7206283 | High-performance network switch The present invention provides a high-performance network switch. A digital switch has a plurality of blades coupled to a switching fabric via serial pipes. Serial link technology is used in the switching fabric. Each blade outputs serial data streams with in-band c... | 04/17/2007 |
| 7206831 | On card programmable filtering and searching for captured network data A programmable data filtering/searching system for use with a data network. The primary programmable hardware-based filtering and searching portions of the system are integrated onto the same printed circuit board as the data storage device to facilitate efficient f... | 04/17/2007 |
| 7206973 | PCI validation A method and system for validating host bus adapters uses two processing passes. In the first pass, a snapshot of all configuration values of selected peripheral devices is taken. Then, the host bus adapter is powered down for a predefined period of time and powered... | 04/17/2007 |
| 7203194 | Method and system for encoding wide striped cells A system and method for encoding wide striped cells that carry packets of data across stripes. The method encodes an initial block of a first wide striped cell is encoded with initial cell encoding information, and distributes initial bytes of packet data into avail... | 04/10/2007 |
| 7200703 | Configurable components for embedded system design A system and method of designing an accelerator for a processor-based system. The accelerator design problem is partitioned into a data communicate module design problem and a data compute core module design problem. The hardware design of the data communicate modul... | 04/03/2007 |
| 7200824 | Performance/power mapping of a die Methods and apparatus are provided for harnessing the effects of process variations in a semiconductor device. In one example, implementing an electronic design based on collected performance parameters is provided. In general, a core is segmented into multiple core... | 04/03/2007 |
| 7200832 | Macro cell for integrated circuit physical layer interface A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of mac... | 04/03/2007 |
| 7197681 | Accelerated scan circuitry and method for reducing scan test data volume and execution time An architecture and methodology for test data compression using combinational functions to provide serial coupling between consecutive segments of a scan-chain are described. Compressed serial-scan sequences are derived starting from scan state identifying desired C... | 03/27/2007 |
| 7197505 | Multi-dimensional recursive wavefront behavioral synthesis A behavioral synthesis process is provided that transforms a generalized behavioral design into a detailed interconnection of design objects to implement the behavior. A design database including design objects is generated as a user creates a diagrammatic represent... | 03/27/2007 |
| 7197734 | Method and apparatus for designing systems using logic regions A method for positioning components of a system onto a target device utilizing programmable logic devices (PLDs) is disclosed. A first location on the target device for a first logic region having a first component is determined. Determined properties of the first l... | 03/27/2007 |
| 7193432 | VPA logic circuits Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first co... | 03/20/2007 |
| 7193737 | Method of storing initial use date of printer and informing the date There is provided a method of storing an initial use date of a printer and informing the initial use date. To store the initial use date, it is determined whether the printer is used for the first time. If the printer is used for the first time, the initial use date... | 03/20/2007 |
| 7193440 | Configurable circuits, IC's, and systems Some embodiments of the invention provide a configurable integrated circuit (IC). The configurable IC includes first and second interconnect circuits. The first interconnect circuit has a set of input terminals, a set of output terminals, and several connection sche... | 03/20/2007 |
| 7193434 | Semiconductor integrated circuit There is provided a high-performance semiconductor integrated circuit whose circuit area is small and whose wiring length is short. The semiconductor integrated circuit is constructed in a multi-layer structure and is provided with a switch block for switching conne... | 03/20/2007 |
| 7194723 | Techniques for mapping functions to lookup tables on programmable circuits Techniques for mapping functions in a user design to lookup tables on a programmable integrated circuit are provided. Functions within a user design are rewritten as a composition of smaller, decomposed functions using a decomposition technique. An attempt is made t... | 03/20/2007 |
| 7193437 | Architecture for a connection block in reconfigurable gate arrays An optimized architecture to implement connections between logic blocks and routing lines in reconfigurable gate arrays including connection blocks to connect inputs and outputs of different logic elements by means of connection wires, each connection block includin... | 03/20/2007 |
| 7194705 | Simulation of integrated circuitry within a high-level modeling system using hardware description language circuit descriptions Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the o... | 03/20/2007 |
| 7194720 | Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined ... | 03/20/2007 |
| 7194721 | Cost-independent criticality-based move selection for simulated annealing A method of physical design for a programmable logic device (PLD) can include associating movable objects of the PLD with a criticality measure that is dependent upon timing information for a configuration of the PLD (115). The method further can include calc... | 03/20/2007 |
| 7194722 | Cost-independent critically-based target location selection for combinatorial optimization A method of physical design for a programmable logic device can include associating target locations for movable objects with criticality measures and calculating the criticality measure for each target location. A probability for each target location can be calcula... | 03/20/2007 |
| 7194600 | Method and apparatus for processing data with a programmable gate array using fixed and programmable processors A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues wh... | 03/20/2007 |
| 7194615 | Reconfigurable apparatus being configurable to operate in a logarithmic scale An integrated circuit has a command/control bus and a number of processing elements. The processing elements contain a number of parts, each part being connected to said command/control bus. Each one of the processing elements is re-configurable in response to comma... | 03/20/2007 |
