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| Number | Title | Issue Date |
| 7886250 | Reconfigurable integrated circuit The purpose of the present invention is to realize reduction of power consumption of reconfigurable integrated circuits such as FPGAs by decreasing leakage current in SRAMs. A reconfigurable integrated circuit is provided which includes transistors and compri... | 02/08/2011 |
| 7877721 | Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are per... | 01/25/2011 |
| 7873934 | Method and apparatus for implementing carry chains on field programmable gate array devices A method for designing a system to be implemented on a field programmable gate array (FPGA) includes identifying an adder from an intermediate representation of the system. Components on the target device are designated to support and implement the adder as a partit... | 01/18/2011 |
| 7870529 | Operational cycle assignment in a configurable IC Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. F... | 01/11/2011 |
| 7870530 | Operational cycle assignment in a configurable IC Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. F... | 01/11/2011 |
| 7861206 | System-on-a-chip for processing multimedia data and applications thereof A system-on-a-chip integrated circuit includes a multimedia module that produces rendered output data and a high-speed interface. A processing module generates output multimedia data in accordance with at least a portion of a multimedia application in response to in... | 12/28/2010 |
| 7856611 | Reconfigurable interconnect for use in software-defined radio systems A method of fabricating an interconnect circuit for coupling a plurality of reconfigurable component blocks that implement a defined function. The method comprises the steps of: 1) determining P possible configurations for implementing the defined function; 2) for e... | 12/21/2010 |
| 7853916 | Methods of using one of a plurality of configuration bitstreams for an integrated circuit Methods of using one of a plurality of configuration bitstreams in an integrated circuit are disclosed. An exemplary method comprises analyzing the plurality of implementations of a design to determine initial variations in timing among the implementations; modifyin... | 12/14/2010 |
| 7849434 | Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Some embodiments provide a method that defines a set of connections that connect the nodes in a configurable node array. The method identifies different sets of connections for connecting a set of the nodes. For each identified set of connections, the method compute... | 12/07/2010 |
| 7849435 | Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utiliz... | 12/07/2010 |
| 7818705 | Method and apparatus for implementing a field programmable gate array architecture with programmable clock skew A skew generator unit includes a delay chain. The delay chain is coupled to a clock line that transmits a clock signal. The delay chain generates a skewed clock signal having a unit of delay from the clock signal. The skew generator unit also includes a selector. Th... | 10/19/2010 |
| 7818706 | Semiconductor integrated circuit device Disclosed is a semiconductor integrated circuit device operated in stability by high-speed clock signals and which is high in a cell using rate and in interconnection efficiency. In a mid part of a chip, there are provided an I/O 11b, supplied with a c... | 10/19/2010 |
| 7797665 | Patterns for routing nets in a programmable logic device Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable int... | 09/14/2010 |
| 7797664 | System for configuring an integrated circuit and method thereof With respect to the reconfigurable integrated circuit, a system for configuring an integrated circuit and a configuration method thereof which do not need a circuit overhead for variation correction and diagnosis of variation are provided. A system for configuring a... | 09/14/2010 |
| 7793251 | Method for increasing the manufacturing yield of programmable logic devices A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each... | 09/07/2010 |
| 7788623 | Composite wire indexing for programmable logic devices Various techniques are described to identify composite wires from segmented wires of a programmable logic device (PLD). In one example, a method includes identifying a plurality of interface templates corresponding to tiles of the PLD. The PLD comprises a plurality ... | 08/31/2010 |
| 7788624 | Methods of balancing logic resource usage in a programmable logic device A computer-implemented method of balancing logic resource usage in a circuit design for a programmable integrated circuit (IC) includes determining that an assignment of elements of the circuit design to a first type of logic resource is unbalanced compared to an as... | 08/31/2010 |
| 7784011 | Reflecting pin swap of PLD performed in package design in circuit design and PLD design An FPGA-information managing unit retrieves FPGA information, such as pin assignment information and attribute information, that is created by an FPGA-designing CAD apparatus. A library creating unit creates a symbol library by using the FPGA information. A pin-swap... | 08/24/2010 |
| 7779380 | Data processing apparatus including reconfigurable logic circuit There is provided a data processing apparatus (1) including a logic circuit (10) that is reconfigurable in each cycle and a library (2) that stores hardware control information (20). The hardware control information (20) includes a... | 08/17/2010 |
| 7765511 | Compensation for performance variation in integrated circuits Various approaches are provided for generating an implementation of an electronic circuit design. In one embodiment, a processor-based method implements a design in an integrated circuit or IC (e.g., a programmable logic device. The method includes storing performan... | 07/27/2010 |
| 7765512 | Relocatable circuit implemented in a programmable logic device A circuit is implemented using a programmable logic device (PLD) that includes an array of programmable logic and routing resources. The circuit includes a processor, a configuration port, a relocatable circuit, and an interface circuit. The processor accesses an ad... | 07/27/2010 |
| 7757198 | Scan chain systems and methods for programmable logic devices Systems and methods provide techniques to support design specific testing for programmable logic devices in accordance with one or more embodiments. For example in one embodiment, a method of generating configuration data for a programmable logic device includes map... | 07/13/2010 |
| 7757197 | Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal... | 07/13/2010 |
| 7739647 | Methods and system for configurable domain specific abstract core The present invention provides a configurable domain specific abstract core (DSAC) for implementing applications within any domain. The DSAC comprises at least one function specific abstract module (FSAM) configurable at a plurality of stages for implementing a pred... | 06/15/2010 |
| 7735045 | Method and apparatus for mapping flip-flop logic onto shift register logic Method and apparatus for mapping flip-flop logic onto shift register logic is described. In one example, a method of processing flip-flop logic in a circuit design for implementation in an integrated circuit is provided. A chain of flip-flops in the circuit design i... | 06/08/2010 |
| 7725867 | Gate-array or field programmable gate array Some Gate Arrays and in particular Filed Programmable Gate Arrays (FPGAs), realize combinatorial logic by utilizing so-called “Look Up Tables” (LUTs). Unfortunaltely the circuit expenditure for a LUT is exponentially increasing with the number of inputs. The inv... | 05/25/2010 |
| 7725868 | Method and apparatus for facilitating signal routing within a programmable logic device Method and apparatus for facilitating signal routing within a programmable logic device having routing resources is described. In an example, the routing resources are formed into groups where, for each of the groups, the routing resources are of a same type. Pairs ... | 05/25/2010 |
| 7716623 | Programmable logic device architectures and methods for implementing logic in those architectures A programmable logic device (“PLD”) architecture includes logic elements (“LEs”) grouped together in clusters called logic array blocks (LABs”). To save area, local feedback resources (for feeding outputs of the LEs in a LAB back to inputs of LEs in the LA... | 05/11/2010 |
| 7716622 | Memory re-implementation for field programmable gate arrays Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are... | 05/11/2010 |
| 7703065 | FPGA with hybrid interconnect An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipli... | 04/20/2010 |
| 7694265 | Operational cycle assignment in a configurable IC Some embodiments provide a method of designing a configurable integrated circuit (“IC”) with several configurable circuits. The method receives a design having several sets of operations for the configurable circuits to perform in different operational cycles. F... | 04/06/2010 |
| 7676783 | Apparatus for performing computational transformations as applied to in-memory processing of stateful, transaction oriented systems An apparatus for performing in-memory computation for stateful, transaction-oriented applications is provided. The apparatus includes a multi-level array of storage cells. The storage cells are configurable for a read access from one of a plurality of access data pa... | 03/09/2010 |
| 7676782 | Efficient method for mapping a logic design on field programmable gate arrays An efficient method for mapping a logic design on Field Programmable Gate Arrays involves a determination of the minimum required square grid of FPGA logic blocks for mapping the design, providing a compensation factor on the minimum square grids, selecting the maxi... | 03/09/2010 |
| 7673272 | Method and apparatus for generating an area constraint for a module in a programmable logic device Method and apparatus for generating an area constraint for a module in a programmable logic device (PLD) is described. In an example, first logic resources are selected in a floorplan of the PLD for implementing a first module of a circuit design. A routing resource... | 03/02/2010 |
| 7673271 | Enhancing relocatability of partial configuration bitstreams Enhancing relocatability of partial configuration bitstreams from a first area to a second area of programmable logic of an integrated circuit is described. A first set and a second set of logic resources of the programmable logic are identified. The first set and t... | 03/02/2010 |
| 7673274 | Datapipe interpolation device A system for data processing comprises a host circuit (104) and an integrated circuit (102). The integrated circuit (102) is in communication with the host circuit (104) and the host circuit (104) is external to the integrated circ... | 03/02/2010 |
| 7673273 | MPGA products based on a prototype FPGA A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads... | 03/02/2010 |
| 7665058 | Customizable development and demonstration platform for structured ASICs The present invention is directed to a customizable development and demonstration platform for structured ASICs. In an exemplary aspect of the present invention, the present platform may include a structured ASIC which is built on a slice and which may be flexible e... | 02/16/2010 |
| 7657861 | Method and device for processing data In a system including a multidimensional field of reconfigurable elements, and a method for operating said field of reconfigurable elements, one or more groups of said elements suitable for processing a predetermined task may be determined, a particular one of the o... | 02/02/2010 |
| 7653891 | Method of reducing power of a circuit A method of reducing power of a circuit is described. The method includes determining at least one unused selection input associated with stages of a multiplexer tree; pulling the at least one unused selection input to a constant value; and assigning predetermined v... | 01/26/2010 |
