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| Number | Title | Issue Date |
| 7886248 | Layout method of semiconductor integrated circuit and computer-readable storage medium storing layout program thereof The present invention is a method that a redundant via is never added afterwards for a signal wiring or a clock wiring, but layout is performed using a multi-cut via from the beginning, which is used for laying out a semiconductor integrated circuit by a step (S3... | 02/08/2011 |
| 7873931 | Congestion-based routing with reconfigurable cross-points for dense signal tapping A computer-implemented method of incorporating probe points within a circuit design for implementation within an integrated circuit device can include routing probe nets of the circuit design in an overlap mode, identifying a plurality of probe net routes including ... | 01/18/2011 |
| 7865861 | Method of generating wiring routes with matching delay in the presence of process variation A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a fir... | 01/04/2011 |
| 7844936 | Method of making an integrated circuit having fill structures A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apar... | 11/30/2010 |
| 7823115 | Method of generating wiring routes with matching delay in the presence of process variation A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a fir... | 10/26/2010 |
| 7823114 | Method of designing wiring structure of semiconductor device and wiring structure designed accordingly A method of designing a wiring structure of an LSI is capable of reducing a capacitance variation ratio ΔC/C or a resistance-by-capacitance variation ratio Δ(RC)/(RC) of the wiring structure. The method sets a process-originated variation ratio (δP) fo... | 10/26/2010 |
| 7793250 | Topology-driven apparatus, method and computer program product for developing a wiring design A method for developing a wiring design for a complex system includes creating a master wire harness network (MWHN) within pathway space reservations of a pathway space-reservation network of the complex system. In this regard, the MWHN can comprise a model of possi... | 09/07/2010 |
| 7747976 | Semiconductor cell with power layout not contacting sides of its rectangular boundary and semiconductor circuit utilizing semiconductor cells A semiconductor cell and a semiconductor circuit utilizing semiconductor cells. The semiconductor cell includes a rectangular boundary and a power layout, where the power layout does not contact any pair of opposite sides of the rectangular boundary. Additionally, t... | 06/29/2010 |
| 7730442 | Apparatus for designing circuit and method for designing circuit according to clearance required between wirings therein An apparatus for designing a circuit comprises an arranging element which arranges a first wiring required a predetermined clearance between the first wiring and other wirings and a second wiring being thinner in a wiring width than the first wiring, a calculating e... | 06/01/2010 |
| 7725864 | Systematic yield in semiconductor manufacture Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tende... | 05/25/2010 |
| 7716621 | Method and system for improving signal integrity in integrated circuit designs A method and system of improving signal integrity in integrated circuit designs is disclosed. In some embodiments, signal integrity optimization is conducted in conjunction with detailed routing of an integrated circuit design based upon a global routing plan previo... | 05/11/2010 |
| 7694264 | Pulse link and apparatus for transmitting data and timing information on a single line A routing block using a switch with a pulsed serial link. An input of a routing block is supplied with an information signal. The routing block has multiple outputs. The information signal includes a first edge and a second edge on a single line. The first and secon... | 04/06/2010 |
| 7600209 | Generating constraint preserving testcases in the presence of dead-end constraints Mechanisms for generating constraint preserving testcases in the presence of dead-end constraints are provided. A balance between precision and computational expense in generating the testcases is achieved by establishing a sliding window of constraint solving for a... | 10/06/2009 |
| 7587696 | Semiconductor device, layout method and apparatus and program A semiconductor device, a layout device and a layout method in which, if the size of a via interconnecting a first conductor provided in an interconnect layer and a second conductor which is provided in an interconnect layer different from the interconnect layer of ... | 09/08/2009 |
| 7568178 | System simulation and graphical data flow programming in a common environment using wire data flow Various embodiments of systems and methods are described in which system simulation techniques are combined with graphical programming techniques in a common environment. For example, various embodiments of the methods comprise displaying a graphical data flow diagr... | 07/28/2009 |
| 7562330 | Budgeting global constraints on local constraints in an autorouter Local constraints on placement of routing objects for direct connections between terminals in a circuit layout are determined from global constraints on the placement of the routing objects in a process referred to as global constraint budgeting. An autorouter finds... | 07/14/2009 |
| 7503026 | Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on r... | 03/10/2009 |
| 7487488 | Predictable repeater routing in an integrated circuit design A mechanism is disclosed for assigning repeaters to signal paths in an integrated circuit design. The mechanism involves reserving, in a first metal layer of the integrated circuit design, metal tracks for routing signals. Access points to a plurality of repeaters a... | 02/03/2009 |
| 7480888 | Design structure for facilitating engineering changes in integrated circuits A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifia... | 01/20/2009 |
| 7464359 | Method for re-routing an interconnection array to improve switching behavior in a single net and an associated interconnection array structure Disclosed are embodiments of an interconnection array for a circuit. The interconnection array comprises a victim net that is positioned parallel to and adjacent to sections of multiple crossed aggressor nets, thereby, minimizing the exposure of the circuit to delay... | 12/09/2008 |
| 7444614 | Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than th... | 10/28/2008 |
| 7444611 | Automatic design method including automatic processing for equalizing spacing wiring and automatic designing apparatus thereof In an area extracting step, areas interposed among tower post rows adjacent to one another, and rectangular areas interposed among the tower post rows and pads at outer peripheral portions of a chip are respectively extracted as areas in which equalization of wire s... | 10/28/2008 |
| 7441220 | Local preferred direction architecture, tools, and apparatus Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different pref... | 10/21/2008 |
| 7437699 | Layout method for semiconductor integrated circuit, layout program for semiconductor integrated circuit and layout system for semiconductor integrated circuit When carrying out placement and routing processing on a layout object circuit using circuit connectivity information and power supply information, a first step of specifying a power supply terminal corresponding to a signal terminal designated for input level fixati... | 10/14/2008 |
| 7434187 | Method and apparatus to estimate delay for logic circuit optimization Methods and apparatuses to estimate delay for logic circuit optimization using back annotated placement and delay data. In one aspect of the invention, a method to design a logic circuit, the method includes: modifying a first path that is back annotated with first ... | 10/07/2008 |
| 7434190 | Analysis method and analysis apparatus of designing transmission lines of an integrated circuit packaging board An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data ... | 10/07/2008 |
| 7434191 | Router Configuration of a reconfigurable multidimensional field may include prioritizing required connections between cells, establishing connections having a high priority first, and establishing additional connections after the high priority connections have been establi... | 10/07/2008 |
| 7428720 | Standard cell for a CAD system In a low power consumption mode in which prior data is retained upon power shutdown, the return speed thereof is increased. While use of an existent data retaining flip-flop may be considered, this is not preferred since it increases area overhead such as enlargemen... | 09/23/2008 |
| 7424695 | Method of manufacturing a semiconductor integrated circuit, a program for a computer automated design system, and a semiconductor integrated circuit A method for manufacturing a semiconductor integrated circuit uses layout data designed by a sequence of processes. The sequence of processes includes disposing a lower-layer wiring pattern on an imaginary lower-layer wiring layer and an upper-layer wiring pattern p... | 09/09/2008 |
| 7421672 | Checks for signal lines Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, det... | 09/02/2008 |
| 7418693 | System and method for analysis and transformation of layouts using situations Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying featur... | 08/26/2008 |
| 7418689 | Method of generating wiring routes with matching delay in the presence of process variation A method and service of balancing delay in a circuit design begins with nodes that are to be connected together by a wiring design, or by being supplied with an initial wiring design that is to be altered. The wiring design will have many wiring paths, such as a fir... | 08/26/2008 |
| 7412682 | Local preferred direction routing Some embodiments of the invention provide a method for routing. The method defines at least one wiring layer that has at least two regions with different local preferred wiring directions. The method then uses the differing local preferred wiring directions to defin... | 08/12/2008 |
| 7412679 | Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method A low-power-consumption type semiconductor integrated circuit incorporating a variety of functions and a semiconductor integrated circuit manufacturing method are provided. As an example of a semiconductor integrated circuit, a system LSI 1 has first circuit ... | 08/12/2008 |
| 7409663 | Process for the production of an electrical wiring diagram This process allows for the automatic production of an electrical wiring diagram on which are located boxes, each representing a component used in an electrical device, connecting lines, each representing an interconnecting cable and connecting terminals correspondi... | 08/05/2008 |
| 7409664 | Architecture and interconnect scheme for programmable logic circuits An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between l... | 08/05/2008 |
| 7404168 | Detailed placer for optimizing high density cell placement in a linear runtime A detailed placement process which optimizes cell placement with up to one hundred percent densities in a linear run time. The output from a conjugate-gradient coarse placement process is input to the detailed placement process. A dynamic programming technique is us... | 07/22/2008 |
| 7404166 | Method and system for mapping netlist of integrated circuit to design The present invention provides a method for mapping a netlist of an integrated circuit to a design. The method includes steps as follows. Chaos algorithm is used to obtain most favorable places in the design for cells from the netlist. Kuhn's algorithm is utilized t... | 07/22/2008 |
| 7398499 | Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design A method of searching paths that are susceptible to electrostatic discharge (ESD) at the beginning of an integrated circuit (IC) design is disclosed that includes a circuit spreading out algorithm, a matrix closure algorithm, and a supernode algorithm. The found pat... | 07/08/2008 |
| 7398498 | Method and apparatus for storing routes for groups of related net configurations Some embodiments of the invention provide a method that pre-computes routes for groups of related net configurations. These routes are used by a router that uses a set of partitioning lines to partition a region of a design layout into a plurality of sub-regions. Th... | 07/08/2008 |
