Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 8015510 | Interconnection modeling for semiconductor fabrication process effects In one embodiment, an interconnect object in a layout of an integrated circuit design to be created with a photolithographic process is determined. The interconnect object includes a width and a length in the layout. A contour generation of the interconnect object i... | 09/06/2011 |
| 7895545 | Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning A method for designing a chip a priori for design subsetting, feature analysis, and yield learning. The method includes identifying a plurality of signal paths within a chip design that can be readily identified from chip fail data and removing a fraction of the plu... | 02/22/2011 |
| 7890909 | Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow An automatic custom block composition tool for composing custom blocks of an integrated circuit (IC) design that may include non-standard library cells. The tool includes program instructions that are executable to create and use a placement control file that includ... | 02/15/2011 |
| 7856610 | Method and apparatus for semiconductor integrated circuit A design method for a semiconductor integrated circuit includes a first step (S13) of grouping pins that configure a same net into a plurality of groups; a second step (S14) of defining sub-trunk wirings mutually connecting the pins that belong to a sa... | 12/21/2010 |
| 7853915 | Interconnect-driven physical synthesis using persistent virtual routing A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with ro... | 12/14/2010 |
| 7844935 | Wiring design system of semiconductor integrated circuit, semiconductor integrated circuit, and wiring design program A wiring design system for semiconductor integrated circuit which realizes a low power consumption in a grid-shaped clock wiring within a semiconductor integrated circuit is provided. A wiring design system 10 for semiconductor integrated circuit which design... | 11/30/2010 |
| 7836422 | System, method and apparatus for optimizing multiple wire pitches in integrated circuit design A method for routing wires in an integrated circuit includes defining an even number n of initial width routing tracks in a selected routing channel. The n initial routing tracks are separated by a substantially equal first separation distance from the other routing... | 11/16/2010 |
| 7818704 | Capacitive decoupling method and module The present invention is directed to a capacitive decoupling module and method for an integrated circuit that features providing multiple capacitive elements to decouple the power rails from the integrated circuit. The multiple capacitive elements are spaced-apart, ... | 10/19/2010 |
| 7814454 | Selectable device options for characterizing semiconductor devices A system, method and program product that allows multiple devices to be placed between pads such that a Back End Of Line (BEOL) mask change can be used to select different device options. A system is disclosed for implementing a testsite for characterizing devices i... | 10/12/2010 |
| 7805697 | Rotary clock synchronous fabric Methods for generating a design for logic circuitry using rotary traveling wave oscillators (RTWOs) are described. A plurality of RTWOs are is arranged into an array of rows and columns. Adjacent elements in the array are interconnected so that the clocks in adjacen... | 09/28/2010 |
| 7797662 | Method and system for design and modeling of transmission lines A method and system for design and modeling of transmission lines are provided. The method includes providing a set of models of core structures (211) of transmission line cells and expanding each of the models of core structures (211) to include diffe... | 09/14/2010 |
| 7784010 | Automatic routing system with variable width interconnect A system automatically routes interconnect of an integrated circuit design using variable width interconnect lines. For example, a first automatically routed interconnect may have a different width from a second automatically routed interconnect. The system will var... | 08/24/2010 |
| 7765510 | Method of searching for wiring route including vias in integrated circuit A wiring design device for an integrated circuit has been disclosed, which is capable of easily changing a via to a redundant via in a route for which search has been completed but which has been found to be changed after the design has advanced and of easily obtain... | 07/27/2010 |
| 7725863 | Reverse routing methods for integrated circuits having a hierarchical interconnect architecture The present invention relates to methods for the global and detail routing of integrated circuits with hierarchical interconnect routing architecture. The methods includes the steps of: mapping routing resources of said integrated circuit to the nodes and edges of a... | 05/25/2010 |
| 7721245 | System and method for electromigration tolerant cell synthesis A method, data processing system, and computer program product are provided for routing a circuit placement a number of times, resulting in a number of routings. An electromigration quality value is computed for each of the routings, and the routing with the best el... | 05/18/2010 |
| 7707537 | Method and apparatus for generating layout regions with local preferred directions Some embodiments of the invention provide a method for defining wiring directions in a design layout having several wiring layers. The method decomposes a first wiring layer into several non-overlapping regions. It assigns at least two different local preferred wiri... | 04/27/2010 |
| 7698680 | Engineering change order cell and method for arranging and routing the same There is provided an engineering change order (ECO) cell, which includes: a function circuit including at least one PMOS transistor with a P-diffusion layer and a first poly gate, at least one NMOS transistor with an N-diffusion layer and a second poly gate; a first... | 04/13/2010 |
| 7694263 | Method of wiring data transmission lines and printed circuit board assembly wired using the method A method of wiring data transmission lines between a CPU including CPU data pins identified by a set of pin numbers and a DRAM including DRAM data pins also identified by the set of pin numbers, the method including connecting the CPU data pins to the DRAM data pins... | 04/06/2010 |
| 7689964 | System and method for routing connections A method for modeling a circuit includes receiving a netlist that defines a plurality of connections between a plurality of circuit elements and identifying a subset of the connections. The method also includes routing the identified connections with a first group o... | 03/30/2010 |
| 7689963 | Double diamond clock and power distribution Systems and methods of double diamond clock and power distribution. In accordance with a first embodiment of the present invention, an integrated circuit comprises a first metallization layer. that is substantially a power plane and a second metallization layer disp... | 03/30/2010 |
| 7685553 | System and method for global circuit routing incorporating estimation of critical area estimate metrics An electronic circuit layout refinement method and system. A grid of equally sized tiles is defined on a circuit layout area. Each tile of the grid has a respective critical area estimate metric associated with critical area estimates for a circuit to be placed on t... | 03/23/2010 |
| 7685552 | Semiconductor integrated circuit device having clock buffers and method for arranging the clock buffers on the device This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the pluralit... | 03/23/2010 |
| 7661086 | Enhanced clock signal flexible distribution system and method A diagonal offset clock signal distribution system and method are presented that facilitate maximized placement of a diagonal offset clock signal distribution tree. ... | 02/09/2010 |
| 7657860 | Method and system for implementing routing refinement and timing convergence Disclosed is an improved method, system, and article of manufacture for implementing routing for an electrical circuit and chip design. A routing architecture can be represented as a spectrum of different granular routing levels. Instead of routing based upon area, ... | 02/02/2010 |
| 7657859 | Method for IC wiring yield optimization, including wire widening during and after routing Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and... | 02/02/2010 |
| 7640524 | Connectivity-based symbol generation in wiring diagrams A computer-implemented method includes inputting a netlist and generating symbols and connections formed according to the netlist and a selected wiring harness layout dimension. A wiring harness diagram is generated along the layout dimension according to the symbol... | 12/29/2009 |
| 7631283 | Methods and apparatus for defining manhattan power grid structures having a reduced number of vias A method for producing a power grid structure (having stripe, rail, and via components) of an IC. The method reduces the number of vias in the power grid structure and the diagonal wiring blockage caused by the vias while still meeting design specifications. Other e... | 12/08/2009 |
| 7577933 | Timing driven pin assignment A mechanism is disclosed for determining pin assignments in an integrated circuit. More particularly, the mechanism involves accessing design information for the integrated circuit. The design information includes a floorplan that sets forth an arrangement of blocks... | 08/18/2009 |
| 7562329 | Master-slice-type semiconductor integrated circuit having a bulk layer and a plurality of wiring layers and a design method therefor In a master-slice-type semiconductor integrated circuit having a bulk layer on which a plurality of bulk patterns to realize specific circuit functions are formed, and a plurality of wiring layers including variable wiring patterns of which wiring pattern is changea... | 07/14/2009 |
| 7543263 | Automatic trace shaping method An automatic trace shaping method comprises the steps of: setting sets of coaxial equiangular octagons each having sides parallel with a predetermined reference line; performing a process for tentatively disposing the traces each having segments passing between the ... | 06/02/2009 |
| 7536667 | Method of semiconductor device and design supporting system of semiconductor device A designing method of a semiconductor device is achieved by setting interconnection reference data indicating permissible interconnection widths which are discrete, and a permissible interval between adjacent two of interconnections, the interconnection intervals be... | 05/19/2009 |
| 7536666 | Integrated circuit and method of routing a clock signal in an integrated circuit The various embodiments of the present invention relate to coupling clock signals between a plurality of data transceivers. According to one embodiment, a clock routing circuit having data transceivers comprises a clock bus interface and a first data transceiver cou... | 05/19/2009 |
| 7530041 | System and method for auto-routing jog elimination A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a width difference between a width of the wire and a width of the source, and dividin... | 05/05/2009 |
| 7530040 | Automatically routing nets according to current density rules A technique will automatically route interconnect of an integrated circuit while taking into consideration current density rules. In an implementation, the technique uses a shape-based approach where a grid is not used. Based on data input including current density ... | 05/05/2009 |
| 7530042 | System and method for auto-routing jog elimination A method for automatic wire size modification comprising the steps of routing a wire to a source; detecting a first size differential between the wire and the source by calculating a first width difference between a length of the wire and a width of the source, and ... | 05/05/2009 |
| 7496878 | Automatic wiring method and apparatus for semiconductor package and automatic identifying method and apparatus for semiconductor package A semiconductor package automatic wiring apparatus which determines an optimum wiring route from each pad to a corresponding one of vias on a semiconductor package having a multi-tier bonding pad structure in which pads to be connected to a semiconductor chip are ar... | 02/24/2009 |
| 7484199 | Buffer insertion to reduce wirelength in VLSI circuits Wirelength in a net of an integrated circuit design is reduced by forming clusters of sinks to be interconnected, inserting a buffer at each cluster, and providing branch connections between clusters by connecting a sink of one cluster to a buffer of another cluster... | 01/27/2009 |
| 7480886 | VLSI timing optimization with interleaved buffer insertion and wire sizing stages The invention relates to layout of circuit components, including determining the interconnections, buffers, or path nets between circuit blocks or circuit components and input/output bonding pads. This is accomplished by a method and program product that optimizes t... | 01/20/2009 |
| 7480887 | Methods and apparatus for defining Manhattan power grid structures beneficial to diagonal signal wiring A method for defining and producing a power grid structure of an IC that minimizes the area of the power grid structure area and the diagonal wiring blockage caused by the power grid structure while still meeting design constraints. A power grid planner is used to d... | 01/20/2009 |
| 7478355 | Input/output circuits with programmable option and related method A chip with programmable input/output (I/O) circuits has a plurality of layout layers including a plurality of same layouts in a plurality of positions of the layout layers so as to implement a plurality of sub-circuit cells with the same layout, and at least a conn... | 01/13/2009 |
