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| Number | Title | Issue Date |
| 8161420 | System and method for security management of home network A security management system of a home network is provided. The home network includes a home gateway and one or more user devices connected to the home gateway. The security management system further includes a security management server adapted to provide a securit... | 04/17/2012 |
| 7890908 | Method for verifying mask pattern data, method for manufacturing mask, mask pattern verification program, and method for manufacturing semiconductor device A method for verifying mask pattern data includes preparing design circuit data on a design circuit which realizes a desired electrical operation. Data on a design circuit pattern having a structure which realizes the design circuit on a semiconductor substrate is p... | 02/15/2011 |
| 7873930 | Methods and systems for optimizing designs of integrated circuits Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking ... | 01/18/2011 |
| 7870528 | Method and system for unfolding/replicating logic paths to facilitate modeling of metastable value propagation A net of an integrated circuit design is analyzed by unfolding paths on the receive side of an asynchronous boundary to facilitate modeling of the propagation of a metastable value from a receive latch to sinks of the net. The paths are unfolded by replicating combi... | 01/11/2011 |
| 7865859 | Implementing APS voltage level activation with secondary chip in stacked-chip technology A method and apparatus implement adaptive power supply (APS) system voltage level activation eliminating the use of electronic Fuses (eFuses), and a design structure on which the subject circuit resides are provided. A primary chip includes an adaptive power supply ... | 01/04/2011 |
| 7865860 | Layout design device and layout method A layout design device according to an exemplary aspect of the present invention is a layout design device for designing layout of an integrated circuit, including a routing section for adjacently wiring a signal line having a high activity rate and a signal line ha... | 01/04/2011 |
| 7865858 | Method, system, and article of manufacture for implementing metal-fill with power or ground connection Disclosed is a method, system, and article of manufacture for a one-pass approach for implementing metal-fill for an integrated circuit. Also disclosed is a method, system, and article of manufacture for implementing metal-fill that is coupled to a tie-off connectio... | 01/04/2011 |
| 7861205 | Spine selection mode for layout editing Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creat... | 12/28/2010 |
| 7861203 | Method and system for model-based routing of an integrated circuit Disclosed is a method, system, and computer program product for implementing model-based floorplanning, layout, placement, and routing. Models are used to guide the placement and routing of polygons on the IC layout based upon predictions of manufacturing variations... | 12/28/2010 |
| 7861204 | Structures including integrated circuits for reducing electromigration effect A design structure including an integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive ... | 12/28/2010 |
| 7853914 | Fanout-optimization during physical synthesis for placed circuit designs A method of implementing a circuit design for a target device can include assigning load pins of a high fanout signal of a placed circuit design into a plurality of windows according to a location of each load pin on the target device. A source of the high fanout si... | 12/14/2010 |
| 7840930 | Signal connection program, method, and device of hierarchical logic circuit Information of a logic circuit including a hierarchical structure and connection target information up to a connection target including a pin or a net via hierarchies of the logic circuit are read, and a tree structure in which a hierarchy is taken as a node and a c... | 11/23/2010 |
| 7823113 | Automatic integrated circuit routing using spines A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs,... | 10/26/2010 |
| 7823112 | Method, software and system for ensuring timing between clocked components in a circuit A method, software, and system for placing circuit elements and routing wires. The method, software, and system generally include the steps of (a) determining a boundary condition for signal paths between components in a circuit, wherein each of the components recei... | 10/26/2010 |
| 7814453 | Process and apparatus for finding paths through a routing space An initial graph of nodes is created within a routing space, and the number and locations of the nodes in the graph are adjusted. Links are created between nodes of the graph, and traces between specified nodes are created through the linked graph. ... | 10/12/2010 |
| 7793249 | Method and system for adaptive bundling of connections in user-guided autorouting Automatic bundle filtering is provided to selectively configure a circuit design having a plurality of component terminals for physical implementation. A placement of components is established for a layout of the circuit design, and a plurality of connections to be ... | 09/07/2010 |
| 7784008 | Performance visualization system A visualization displays user designs and performance information at different levels of detail. Related register bits are combined into a metaregister and displayed as a graph node. The set of paths and associated combinatorial logic between two or more metaregiste... | 08/24/2010 |
| 7784009 | Electrically programmable π-shaped fuse structures and design process therefore Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion ... | 08/24/2010 |
| 7779379 | Template-based gateway model routing system A routing tool allows a user to create a set of routing templates, each specifying the shape of a routing corridor and identifying the corridor's terminal edges. Each routing template also specifies a set of constraints on routing of an unspecified number of conduct... | 08/17/2010 |
| 7774734 | Enhanced reach-based graph processing using shortcuts An algorithm referred to as REAL for the point-to-point shortest path problem combines A* search with landmark-based lower bounds and reach-based pruning. A symbiosis of these techniques is described, which gives a range of time and space tradeoffs, including those ... | 08/10/2010 |
| 7765509 | Auto connection assignment system and method A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plur... | 07/27/2010 |
| 7761836 | Circuit autorouter with object oriented constraints In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (... | 07/20/2010 |
| 7757196 | Optimizing application specific integrated circuit pinouts for high density interconnect printed circuit boards Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be ... | 07/13/2010 |
| 7752590 | Method and mechanism for implementing tessellation-based routing Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a port... | 07/06/2010 |
| 7735043 | Wiring layout apparatus, wiring layout method, and wiring layout program for semiconductor integrated circuit A wiring layout apparatus includes a layout design unit configured to design a wiring layout for a semiconductor integrated circuit; a critical wiring detection unit configured to analyze a delay of signal propagation in the wiring layout so as to detect wiring stri... | 06/08/2010 |
| 7730440 | Clock signal distribution system and method A diagonal offset clock signal distribution system and method are presented that facilitate maximized placement of a diagonal offset clock signal distribution tree. ... | 06/01/2010 |
| 7730441 | Method and system for distributing clock signals on non manhattan semiconductor integrated circuit using parameterized rotation The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recurs... | 06/01/2010 |
| 7725860 | Contact mapping using channel routing A technique for improved mapping of the contacts of a PLD to the contacts of one or more other electronic components are provided. In one particular exemplary embodiment, the technique may be realized as a method for mapping contacts of a programmable logic device (... | 05/25/2010 |
| 7725861 | Method, apparatus, and system for LPC hot spot fix Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method for creating a layout from a circuit design is described. The method includes applying a first set of hot spot con... | 05/25/2010 |
| 7725862 | Signal routing on redistribution layer A method of routing signals within a semiconductor memory device includes providing a semiconductor wafer having a top surface with a center portion, an edge portion and wafer bond pads at the center portion. A redistribution layer is provided on the top surface of ... | 05/25/2010 |
| 7721244 | LSI circuit designing system, antenna damage preventing method and prevention controlling program used in same An LSI (Large-Scale Integrated) circuit system capable of preventing antenna damage occurring in MOS (Metal Oxide Semiconductor) transistors due to an erroneous operation of a wiring formed during manufacturing processes of LSIs or like as an antenna. Layout data af... | 05/18/2010 |
| 7721242 | Nanotube circuit analysis system and method Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. ... | 05/18/2010 |
| 7721243 | Method and apparatus for routing Some embodiments of the invention provide a router that can define a route that has different widths along different directions on the same layer. To facilitate the creation of such a route, some embodiments adaptively define the shape of interconnect-line ends (i.e... | 05/18/2010 |
| 7716620 | Moment-based method and system for evaluation of metal layer transient currents in an integrated circuit A moment-based method and system for evaluation of metal layer transient currents in an integrated circuit provides a computationally efficient evaluation of transient current magnitudes through each interconnect in the metal layer. The determinable magnitudes inclu... | 05/11/2010 |
| 7712067 | Method and apparatus for facilitating effective and efficient optimization of short-path timing constraints A method for connecting a first and second component in a logic device is disclosed. A path is generated between the first and second components with an appropriate amount of delay to satisfy short-path timing constraints that define a minimum delay on the path. A f... | 05/04/2010 |
| 7707536 | V-shaped multilevel full-chip gridless routing A router organizes an IC area into an array of global routing cells (GRCs) and generates a congestion map providing a separate congestion factor for each GRC boundary. The router then iteratively partitions the IC area into progressively smaller tiles while selectin... | 04/27/2010 |
| 7698679 | Method and apparatus for automatic routing yield optimization A method is provided for optimizing routing on a substrate such as an integrated circuit or printed circuit board. The method defines a plurality of parallel strips on an initial routing layout of conductors for a layer of an integrated circuit. Each conductor withi... | 04/13/2010 |
| 7694261 | Method and mechanism for implementing tessellation-based routing Disclosed are methods and mechanisms for implementing tessellation-based processing of an integrated circuit design. Tessellation based routing of objects on an integrated circuit layout can be performed by identifying a spacing rule for tessellating at least a port... | 04/06/2010 |
| 7694262 | Deep trench capacitor and method of making same A trench capacitor, method of forming a trench capacitor and a design structure for a trench capacitor. The trench capacitor including: a trench in a single-crystal silicon substrate, a conformal dielectric liner on the sidewalls and the bottom of the trench; an ele... | 04/06/2010 |
| 7694260 | Semiconductor integrated circuit, layout method, layout apparatus and layout program An intermediate wiring layer, lowermost vias and uppermost vias of a semiconductor integrated circuit are disposed within a zone of wiring tracks, which are superposed by wiring traces of an uppermost wiring layer and wiring traces of a lowermost wiring layer, as se... | 04/06/2010 |
