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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 7904849 | Ceramic package in which far end noise is reduced using capacitive cancellation by offset wiring A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi... | 03/08/2011 |
| 7890907 | Computer program product for designing memory circuits having single-ended memory cells with improved read stability A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first a... | 02/15/2011 |
| 7882476 | Semiconductor integrated circuit device formed by automatic layout wiring by use of standard cells and design method of fixing its well potential Standard cells without a well potential fixing active region (4T-11 to 4T-14, 4T-21 to 4T-24, 4T-31 to 4T-34, 4T-41 to 4T-44) are read from a library and a circuit is temporar... | 02/01/2011 |
| 7873929 | Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction Method and apparatus for designing an integrated circuit. A new layout is generated for at least one standard cell that incorporates an auxiliary pattern on a gate layer to facilitate cell-based optical proximity correction. An original placement solution is modifie... | 01/18/2011 |
| 7853913 | Minimizing number of masks to be changed when changing existing connectivity in an integrated circuit A method and apparatus for fabricating integrated circuits providing a desired operation using a plurality of masks, wherein each of said plurality of masks is used to control a corresponding one of a plurality of layers to form said integrated circuits. Said method... | 12/14/2010 |
| 7849432 | Shallow trench isolation dummy pattern and layout method using the same A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outs... | 12/07/2010 |
| 7844934 | Method for designing a semiconductor integrated circuit layout capable of reducing the processing time for optical proximity effect correction According to the present invention, a method for designing a semiconductor integrated circuit layout comprises the steps of: arranging basic logic cells which are circuit patterns corresponding to logic components of a semiconductor integrated circuit; arranging wir... | 11/30/2010 |
| 7840928 | Circuit design tools with optimization assistance Computer aided design tools are provided that assist circuit designers in optimizing circuit performance. A circuit designer who is designing an integrated circuit may supply circuit design data and constraint data. Computer aided design tools may process the data t... | 11/23/2010 |
| 7836421 | Semiconductor layout design apparatus and method for evaluating a floorplan using distances between standard cells and macrocells A semiconductor layout design apparatus has an inter-block connection information extracting part, a cell initial placement part and an evaluation value. The inter-block connection information extracting part configured to extract the number of wiring connections be... | 11/16/2010 |
| 7831947 | Semiconductor layout design apparatus, semiconductor layout design method and computer readable medium A semiconductor layout design apparatus has an inter-block connection information extracting part, a block global placement part and a cell placement setting part. The inter-block connection information extracting part configured to extract the number of wiring conn... | 11/09/2010 |
| 7827512 | Semiconductor device and method of designing the same A plurality of internal circuits (11 to 14) are formed on a semiconductor chip 10, and receive different power supply voltages. An ESD protection circuit (15) is connected to the power supply lines (31 to 34) for the interna... | 11/02/2010 |
| 7827513 | Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs A method for identifying and modifying, in a VLSI hierarchical chip design, parent buffer placements which lead to wiring track inefficiencies with respect to data flow and the parent placement area geometry. Parent placement area is reviewed and a subset is categor... | 11/02/2010 |
| 7818703 | Density driven layout for RRAM configuration module A system for layout of a module in an integrated circuit layout pattern has a cell library and a cell placement system. The cell library includes a plurality of cells. The cell placement system is adapted to select one or more cells from the cell library and to loca... | 10/19/2010 |
| 7802219 | Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates re... | 09/21/2010 |
| 7802220 | Method for effective placement of on-chip decoupling capacitors determined by maximum effective radii The maximum effective radii of an on-chip decoupling capacitor based on a target impedance (discharge) and charge time are determined. To be effective, an on-chip decoupling capacitor should be placed such that both the power supply and the current load are located ... | 09/21/2010 |
| 7802218 | Layout analysis method and apparatus for semiconductor integrated circuit A method for analyzing a layout for a semiconductor integrated circuit, which includes a plurality of physical devices, to generate physical parameter distribution enabling accurate recognition of changes in transistor characteristics caused by systematic variations... | 09/21/2010 |
| 7797660 | Semiconductor integrated circuit for controlling substrate bias A semiconductor integrated circuit device which is improved in wiring efficiency and area efficiency. Metal layers having respective portions protruding out from an N-type diffusion layer and a P-type diffusion layer in plan view toward respective sides of the diffu... | 09/14/2010 |
| 7793247 | Method and apparatus for directed physical implementation of a circuit design for an integrated circuit Method, apparatus, and computer readable medium for directed physical implementation of a circuit design for an integrated circuit is described. One aspect of the invention relates to implementing a circuit design for an integrated circuit. Matching elements between... | 09/07/2010 |
| 7788619 | Memories, memory compiling systems and methods for the same A method of compiling a memory for layout by computation includes inputting memory specification, determining a disposition structure of input/output pads with reference to the memory specification, and creating a layout of the memory in accordance with the determin... | 08/31/2010 |
| 7788620 | Input/output placement systems and methods to reduce simultaneous switching output noise Systems and methods provide I/O signal placement algorithms, such as for a programmable logic device. For example, a performing input/output (I/O) signal placement to pins of an electronic device, in accordance with an embodiment, includes placing all pre-assigned I... | 08/31/2010 |
| 7774732 | Method for radiation tolerance by automated placement A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on ... | 08/10/2010 |
| 7765504 | Design method and system for minimizing blind via current loops A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are chec... | 07/27/2010 |
| 7765505 | Design rule management method, design rule management program, rule management apparatus and rule verification apparatus Disclosed is a rule management apparatus which acquires a design rule for regulating a part shape from systems such as a CAD system 401, converts the acquired deign rule into data having a hierarchical node format, calculates relationship strength which indic... | 07/27/2010 |
| 7761832 | Method for incremental, timing-driven, physical-synthesis optimization under a linear delay model A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a re... | 07/20/2010 |
| 7761831 | ASIC design using clock and power grid standard cell An integrated power and clock grid which is capable of being placed and routed using ASIC software design tools. The integrated grid comprises three types of grid unit cells having power rails and clock lines. The power rails and clock lines comprise different orien... | 07/20/2010 |
| 7761833 | Semiconductor device and dummy pattern arrangement method A semiconductor device includes a plurality of wiring patterns arranged in a first wiring layer of the semiconductor device and extending in a first direction, and a plurality of dummy patterns arranged in the first wiring layer and extending in a second direction d... | 07/20/2010 |
| 7757195 | Methods and systems for implementing dummy fill for integrated circuits A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing proc... | 07/13/2010 |
| 7752587 | Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro ... | 07/06/2010 |
| 7752588 | Timing driven force directed placement flow Techniques for placement of integrated circuit elements include global placement, detailed placement, timing closure, and routing. The integrated circuit is described by a netlist specifying interconnections of morphable devices. The detailed placement uses, for exa... | 07/06/2010 |
| 7747974 | Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure A method and apparatus for optimizing body bias connections to NFETs and PFETs using a deep n-well grid structure. A deep n-well is formed below the surface of a CMOS substrate supporting a plurality of NFETs and PFETs having a nominal gate length of less than 0.2 m... | 06/29/2010 |
| 7743356 | Method of disposing dummy pattern A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the int... | 06/22/2010 |
| 7735041 | Methods and computer readable media implementing a modified routing grid to increase routing densities of customizable logic array devices Disclosed are a method and a computer readable medium for increasing routing density in cells of a customizable logic array device. In one embodiment, the method includes modifying a connectivity grid for manufacturing the customizable logic array device to form a n... | 06/08/2010 |
| 7735042 | Context aware sub-circuit layout modification A method, system and program product for context aware sub-circuit layout modification are disclosed. The method may include defining at least one context for the sub-circuit for each circuit that uses the sub-circuit; in the case that a plurality of contexts are de... | 06/08/2010 |
| 7721239 | Semiconductor integrated circuit with connecting lines for connecting conductive lines of a memory cell array to a driver A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes... | 05/18/2010 |
| 7721240 | Systematic yield in semiconductor manufacture Three-dimensional structures are provided which improve manufacturing yield for certain structures in semiconductor devices. The three-dimensional structures take into account the interaction between an upper layer and a lower layer where the lower layer has a tende... | 05/18/2010 |
| 7712066 | Area-efficient power switching cell A power switching circuit is provided for use in an integrated circuit including at least a first voltage rail and a second voltage rail. The power switching circuit includes at least one MOS device having a first source/drain adapted for connection to the first vol... | 05/04/2010 |
| 7703063 | Implementing memory read data eye stretcher A method and data receiver apparatus implement a high speed, such as double data rate (DDR), memory read data eye stretcher. Altering the reference level is performed to increase the size of the data eye. Knowledge of the previous data state is used to adjust the re... | 04/20/2010 |
| 7698678 | Methodology for automated design of vertical parallel plate capacitors Apparatus and program product for designing vertical parallel plate (VPP) capacitor structures in which the capacitor plates in different conductive layers of the capacitor stack have a different physical spacing. The methodology optimizes the physical spacing of th... | 04/13/2010 |
| 7698677 | On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise A semiconductor power network (100) decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires (420... | 04/13/2010 |
| 7694257 | Method and apparatus for deep sub-micron design of integrated circuits A technique for adding filler metal polygons in metal layers on a chip area of an IC design. In one example embodiment, this is accomplished by computing a size of a filler metal polygon using chip design layout data. One or more regions on the metal layers of the I... | 04/06/2010 |
