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| Number | Title | Issue Date |
| 7360189 | Method and apparatus for enabling waveform display in a system design model A method for generating a waveform display includes retrieving signal data associated with a node in a system design model from a system level electronic design automation tool. A value change dump file that describes the signal data is generated. ... | 04/15/2008 |
| 7360205 | Minimizing interaction costs among components of computer programs A system and method for minimizing total cost of interaction among components of a computer program which are each characterized by at least one implementation property. A implementation property may, for example, be a choice of string representation (e.g. ASCII, UN... | 04/15/2008 |
| 7360066 | Boolean processor A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, a plurality of input/output interfaces, wherein the plurality of input/outpu... | 04/15/2008 |
| 7360182 | Method and system for reducing delay noise in an integrated circuit A method and a system for reducing delay noise in an integrated circuit (IC) includes generating delay information for each net, and each device of the IC. Each net has a ground capacitance, a coupling capacitance, and a resistance. An effective capacitance is compu... | 04/15/2008 |
| 7360007 | System including a segmentable, shared bus A system includes a bus shared by a plurality of devices and a logic circuit adapted to segment the bus into a plurality of portions. In one embodiment of the present invention, the system may include a plurality of devices and a first multiplexer logic circuit adap... | 04/15/2008 |
| 7356782 | Voltage reference signal circuit layout inside multi-layered substrate A multi-layered substrate has a voltage reference signal circuit layout therein. A major change in the design of the multi-layered substrate is the moving of a reference signal trace from a signal layer to a non-signaling layer. Once the reference signal trace is mo... | 04/08/2008 |
| 7356796 | Method and apparatus to boost high-speed I/O signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so th... | 04/08/2008 |
| 7356799 | Timing exact design conversions from FPGA to ASIC Timing exact design conversions from an original field programmable device to an application specific device is disclosed. In a first aspect, a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC) compris... | 04/08/2008 |
| 7356797 | Logic transformation and gate placement to avoid routing congestion A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic ... | 04/08/2008 |
| 7356794 | System and method for designing a delayer emulation model A system for designing a delayer emulation model (1) includes a delayer emulation model generating apparatus (2). The delay emulation model generating apparatus includes: a delay circuit defining module (20) for defining delay parameters of a de... | 04/08/2008 |
| 7356784 | Integrated synthesis placement and routing for integrated circuits A method determining an IC (integrated circuit) design includes: determining one or more design variables, wherein the one or more design variables include one or more device variables and one or more weights; determining one or more net lengths and one or more layo... | 04/08/2008 |
| 7356785 | Optimizing IC clock structures by minimizing clock uncertainty A process is provided for optimizing a clock net in the form of a tree having a root defined by a driver pin and a plurality of leaves defined by driven pins. The process includes forcing a first buffer to a center of gravity of the plurality of leaves, inserting a ... | 04/08/2008 |
| 7356786 | Method and user interface for debugging an electronic system Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with... | 04/08/2008 |
| 7356781 | Method for modifying design data for the production of a component and corresponding units A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered geometrical design, for example through relocations in a region. For the two designs, assessment criteria are asc... | 04/08/2008 |
| 7353471 | Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physi... | 04/01/2008 |
| 7353496 | Storage controller software development support system and software development support method In the present invention, the scope and degree of the effect of hardware alterations on software is grasped, and development is performed while making coordination between software and hardware. The storage system comprises a plurality of hardware elements and a plu... | 04/01/2008 |
| 7353490 | Power network synthesizer for an integrated circuit design A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the s... | 04/01/2008 |
| 7350717 | High speed smart card with flash memory A card and reader system is provided enabling larger storage capacity and faster data transmission. The card is configured in a Smart Card or SIM card format and communicates with either standard Smart Card readers or specially configured readers capable of higher d... | 04/01/2008 |
| 7353468 | Secure exchange of information in electronic design automation Information related to electronic design automation may be exchanged in a secure manner. Information deemed sensitive and otherwise worthy of protection may be secured by methods such as encryption, obfuscation and other security measures. The secured information ma... | 04/01/2008 |
| 7353476 | System, method and computer program product for designing connecting terminals of semiconductor device A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O... | 04/01/2008 |
| 7353473 | Modeling small mosfets using ensemble devices A method of modeling statistical variation of field effect transistors having fingers physically measures characteristics of existing transistors and extracts a scaled simulation based on the characteristics of the existing transistors using a first model. The metho... | 04/01/2008 |
| 7353159 | Method for parallel simulation on a single microprocessor using meta-models The present invention generally relates to hardware development and design, and in particular it relates to a method for simulating hardware. A meta model (22) is compiled for integrating a plurality of n different instantiations (12A, . . . 12N... | 04/01/2008 |
| 7351660 | Process for producing high performance interconnects A method for fabricating high performance vertical and horizontal electrical connections in a three dimensional semiconductor structure. A dielectric film is imprinted with a stamp pattern at high vacuum and with precise temperature and stamping pressure control. Th... | 04/01/2008 |
| 7352862 | Encryption method, communication system, transmission device, and data input device An encryption method includes the steps of (a) generating random data including a first part and a second part, the first part specifying an operation to be performed on plain text data and the second part being used in the operation, (b) performing the specified op... | 04/01/2008 |
| 7353489 | Determining hardware parameters specified when configurable IP is synthesized An attribute of a hardware feature to be customized in a soft core is parameterized so that a value received from a user can be used to generate a description of a circuit containing the customized hardware feature. The generated description also describes, in accor... | 04/01/2008 |
| 7352206 | Integrated circuit device having state-saving and initialization feature An integrated circuit device has a state-saving feature and includes a programmable logic block, I/O pads, a dedicated register, at least one volatile memory block, a non-volatile memory block, a condition-sensing circuit for detecting at least one condition, A cont... | 04/01/2008 |
| 7353467 | Method and system for facilitating electronic circuit and chip design using remotely located resources A multi-faceted portal site acts as a server in the context of an n-tier client/server network, and connects electronic designers and design teams to design and verification tool and service providers on the other through a single portal site. Tools and services acc... | 04/01/2008 |
| 7353481 | Computer implemented method for designing a semiconductor integrated circuit and a semiconductor integrated circuit A computer implemented method for designing a semiconductor integrated circuit includes placing dummy pattern on a second interconnection layer positioned just above the first power line based on a placement result of the first power line, the dummy pattern having a... | 04/01/2008 |
| 7353163 | Exception handling method and apparatus for use in program code conversion A method of handling exceptions for use in an emulator (20) performing program code conversion. Registers (X) of a subject machine (11) being emulated (20) are represented by a pair of abstract registers (XA,XB) on the targ... | 04/01/2008 |
| 7350161 | System design tools A system design method for designing bus-based systems is described. The method includes automatically defining an allowed set of parameter values for the system components concerned. ... | 03/25/2008 |
| 7350160 | Method of displaying a guard ring within an integrated circuit The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guar... | 03/25/2008 |
| 7350072 | Remote management and provisioning of a system across a network based connection An attestation identity key (AIK) is created and stored in a client computer's firmware. When the client computer is connected to a network for the first time, the AIK allows a provisioning server to determine if the client computer has been tampered with. This atte... | 03/25/2008 |
| 7350013 | Bus communication apparatus for programmable logic devices and associated methods A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry ... | 03/25/2008 |
| 7350163 | System and method for automatically calculating parameters of an MOSFET A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating system is used for receiving values inputted, and for calculating parameters of the MOSFET according to the in... | 03/25/2008 |
| 7350164 | Optimization and design method for configurable analog circuits and devices Optimization design method for configurable analog circuits and devices resulting from same. An implementation fabric for a given application domain can be accurately pre-characterized in terms of devices and parasitics. Customization structures are designed and cha... | 03/25/2008 |
| 7350183 | Method for improving optical proximity correction A method for performing model based optical proximity correction (MBOPC) and a system for performing MBOPC is described, wherein the process model is decomposed into a constant process model term and a pattern dependent portion. The desired wafer target is modified ... | 03/25/2008 |
| 7350162 | Structure analytic program A structure analytic program is used to direct a computer to perform a process of analyzing the structure of a HDL data circuit, and efficiently analyzes a design product relating to a circuit design using a hardware description language (HDL) with the configuration... | 03/25/2008 |
| 7350180 | Search algorithm for inheriting clock contexts in hardware description language translation tools A search algorithm supports inherited clock contexts within functions written in a Hardware Description Language. For each function, a parser generates a corresponding node tree. Each clock context node has an associated clock signal and active clock edge. The edge ... | 03/25/2008 |
| 7349329 | Network system, data transmitter-receiver and failure location/compensation method A data transmitter-receiver 30 arranged on a ring network to form a node includes a normal-direction data transmit/receive unit 19, a reverse-direction data transmit/receive unit 20, a buffer control unit 13, a controller 14, and c... | 03/25/2008 |
| 7348678 | Integrated circuit package to provide high-bandwidth communication among multiple dice A system may include a microprocessor die, an integrated circuit package substrate, and a die disposed between the microprocessor die and the integrated circuit package substrate. In some embodiments, the integrated circuit package substrate defines a first cavity, ... | 03/25/2008 |
