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| Number | Title | Issue Date |
| 7430725 | Suite of tools to design integrated circuits A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the... | 09/30/2008 |
| 7430727 | Hardware component graph to hardware description language translation method An HCG to HDL translation method, which can automatically generate VHDL codes. The method reads a hardware component graph (HCG) to find a start node and obtain a corresponding hardware component subgraph of the start node, analyzes all information of the start node... | 09/30/2008 |
| 7428715 | Hole query for functional coverage analysis Functional coverage techniques during design verification using cross-product coverage models and hole analysis are enhanced by the use of coverage queries. After running a test suite, a core set of non-covered events is specified. A coverage query is then automatic... | 09/23/2008 |
| 7428713 | Accelerated design optimization A system, method, and software product for an accelerated design optimization is described. Engineers/designers/users define an initial design with a set of responses and constraints on the responses in a design optimization process. A plurality of approximations to... | 09/23/2008 |
| 7426709 | Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system An FPGA design system includes the use of constraints in order to determine whether to associate arbitration logic with a bus or in slave modules. In one embodiment, area constraints can be used to determine whether a smaller design using arbitration logic at the bu... | 09/16/2008 |
| 7426461 | Method, system and program product for providing a configuration specification language supporting incompletely specified configuration entities In a hardware definition language (HDL) file among one or more files, one or more design entities containing a functional portion of a digital system are specified. The one or more design entities logically contain a plurality of latches having a respective pluralit... | 09/16/2008 |
| 7424687 | Method and apparatus for mapping design memories to integrated circuit layout A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the ... | 09/09/2008 |
| 7424696 | Power mesh for multiple frequency operation of semiconductor products The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher fr... | 09/09/2008 |
| 7424655 | Utilizing multiple test bitstreams to avoid localized defects in partially defective programmable integrated circuits Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices, thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utiliz... | 09/09/2008 |
| 7421672 | Checks for signal lines Some embodiments provide identification of a first polyline and a second polyline associated with a differential signal, determination of whether a distance between a segment of the first polyline and a segment of the second polyline is within a first tolerance, det... | 09/02/2008 |
| 7421667 | System and method for enabling a vendor mode on an integrated circuit A system and method for enabling a vendor mode on an integrated circuit. A method is disclosed for applying a potential to a no-connect pin, whose function is unknown to the customer, to prevent the accidental enabling of the vendor mode. Applying the potential to t... | 09/02/2008 |
| 7421382 | Data analysis techniques for dynamic power simulation of a CPU A method for data analysis of power modeling for a microprocessor has been developed. The method takes multiple values of power data from a power modeling simulator and generates summary data to characterize the power data behavior. Summary data views include result... | 09/02/2008 |
| 7418692 | Method for designing structured ASICS in silicon processes with three unique masking steps A multi-function core base cell includes a set of functional microcircuits. These microcircuits are used to design a Library of Logic Function Macros. The functional macros consisting of one or more microcircuits have a fixed and complete physical layout similar to ... | 08/26/2008 |
| 7418683 | Constraint assistant for circuit design A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types requiring special IC layout constraints. Subcircuit types are identifie... | 08/26/2008 |
| 7418305 | Method of generating a component of a component-based automation system A computer-implemented method for generating a description of a component of an automation system comprises describing the component as a plurality of inputs and outputs, generating a vendor-independent component description file based on a description of the compon... | 08/26/2008 |
| 7418603 | Mobile terminal, circuit board, circuit board design aiding apparatus and method, design aiding program, and storage medium having stored therein design aiding program The present invention provides a tamper resistant circuit board, an apparatus and method for aiding the design of the circuit board, a computer readable storage medium having stored therein a program for performing the method, and a mobile terminal containing the ci... | 08/26/2008 |
| 7415693 | Method and apparatus for reducing synthesis runtime A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second s... | 08/19/2008 |
| 7415683 | Method and apparatus for a chaotic computing module A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically c... | 08/19/2008 |
| 7415691 | Method and system for outputting a sequence of commands and data described by a flowchart The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as ... | 08/19/2008 |
| 7415678 | Method and apparatus for synthesis of multimode X-tolerant compressor Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described. ... | 08/19/2008 |
| 7415680 | Power managers for an integrated circuit A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated ... | 08/19/2008 |
| 7415679 | System and method for selecting MOSFETs suitable for a circuit design The present invention provides a computer-based method for selecting MOSFETs suitable for a circuit design. The method includes the steps of: providing a database (18) that stores specifications and product information of various MOSFETs; receiving specificat... | 08/19/2008 |
| 7412668 | Integrated system noise management—decoupling capacitance A method for noise suppression for a system implementation of an integrated circuit design is described. First clock operating parameters for logic blocks of the integrated circuit design are obtained. Second clock operating parameters for input/output banks of the ... | 08/12/2008 |
| 7412669 | Generation of graphical design representation from a design specification data file Method and apparatus are described for generating a block diagram of an electronic circuit design. In one embodiment, each instance of a multi-master bus, a bus master of a multi-master bus, a bus slave of a multi-master bus, a memory, a co-processor and an input/ou... | 08/12/2008 |
| 7412677 | Detecting reducible registers Reducible registers are determined to optimize a sequential circuit. A screening method tests one or more sets of registers where the registers of each set are assumed to satisfy a logic condition. The tests determine if the logic condition holds. If the logic condi... | 08/12/2008 |
| 7412681 | DC path checking in a hierarchical circuit design A computer implemented method is provided for use in evaluating a hierarchical representation of a circuit design encoded in a computer readable medium comprising: traversing a circuit path within a higher level circuit that includes a reference potential connection... | 08/12/2008 |
| 7409649 | System and method for automatically calculating parameters of an MOSFET A system for automatically calculating parameters of an MOSFET is disclosed. The parameter calculating system runs in a computer. The parameter calculating system is used for receiving values input by the users, and for calculating parameters of the MOSFET according... | 08/05/2008 |
| 7409648 | Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit The semiconductor integrated circuit capable of reducing an interconnection width as compared with conventional one while suppressing electromigration effectively. An input unit 101 stores interconnection information in an interconnection information storage ... | 08/05/2008 |
| 7409658 | Methods and systems for mixed-mode physical synthesis in electronic design automation Methods and systems for electronic design automation includes clustering objects into more manageable numbers of objects. Clustering is optionally performed to reduce or minimize interconnections between clusters. Clustering optionally includes multi-level clusterin... | 08/05/2008 |
| 7409667 | Techniques for modeling a circuit board structure A technique generates circuit board modeling data for a circuit board structure having multiple layers. The technique includes receiving a set of global circuit board dimension parameters from a user. The set of global circuit board dimension parameters defines a se... | 08/05/2008 |
| 7409640 | Electronic service manual for product constituted by electric or electronic circuit A technique for performing an information search relate to parts included in a circuit diagram or a board diagram displayed on a display screen. Network connection destination information, which includes URL information for a predetermined server, a type of informat... | 08/05/2008 |
| 7406674 | Method and apparatus for generating microcontroller configuration information A method and apparatus for configuring a microcontroller. An XML description of the microcontroller's hardware resources may be accessed. A user may select from available hardware resources and pre-defined user modules to select a configuration. Configuration inform... | 07/29/2008 |
| 7406672 | Method and apparatus for constructing and optimizing a skew of a clock tree An apparatus for supporting a design of a circuit including a plurality of elements, comprising: an acquiring unit that acquires a clock tree of the circuit; a constructing unit that constructs, based on the clock tree, a plurality of groups each of which includes a... | 07/29/2008 |
| 7404155 | Merging multiplexers to reduce ROM area Systems and method for reducing the die area occupied by a programmable logic device are provided. The systems and methods relate to a programmable logic device comprising a plurality of multiplexers. A portion of the multiplexers form a multiplexer cone. The cone i... | 07/22/2008 |
| 7404157 | Evaluation device and circuit design method used for the same There is provided an evaluation apparatus capable of measuring the I-V characteristic in the MOSFET AC operation with a high accuracy. There are also provided a circuit design method and a circuit design system used for the evaluation apparatus. In the evaluation ap... | 07/22/2008 |
| 7404154 | Basic cell architecture for structured application-specific integrated circuits A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits ar... | 07/22/2008 |
| 7404158 | Inspection method and inspection apparatus for semiconductor integrated circuit In a semiconductor integrated circuit inspection method of inspecting a semiconductor integrated circuit including plural transistors according to which a test pattern generated for the semiconductor integrated circuit is input to an input terminal of the semiconduc... | 07/22/2008 |
| 7404159 | Critical area computation of composite fault mechanisms using Voronoi diagrams Disclosed is a method that determines critical areas associated with different types of fault mechanisms in an integrated circuit design. The invention does this by constructing individual Voronoi diagrams for critical areas of individual fault mechanisms and a comp... | 07/22/2008 |
| 7404153 | Method for the providing of a design, test and development environment and system for carrying out said method In order to improve the functionality of a computer-assisted design, test and/or development environment for a data processing circuit arrangement, the instructions of the circuit arrangement are stored in a machine-readable manner in a data base with the binary rep... | 07/22/2008 |
| 7404170 | System level applications of adaptive computing (SLAAC) technology An API (Application Programming Interface) for an adaptive computing system (ACS) may be used to create a system for performing an application on different types of ACS platforms. The API may be used to generate a system object including a host and a number of nodes... | 07/22/2008 |
