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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 7334199 | System and method for breaking a feedback loop using a voltage controlled voltage source terminated subnetwork model A system and method is disclosed for breaking a feedback loop by replacing at least one component in the feedback loop with a model containing two physically disconnected subnetworks that have terminals that are connected to ground with voltage controlled, voltage s... | 02/19/2008 |
| 7334152 | Clock switching circuit A clock switching circuit comprises: a composite clock generation circuit, which is to receive a first clock, a second clock, and a clock switching execution signal for switching between the first clock and the second clock, and to make a level of the clock fixed to... | 02/19/2008 |
| 7332380 | Pattern design method and program of a semiconductor device including dummy patterns According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy ... | 02/19/2008 |
| 7334205 | Optimization of die placement on wafers A method of optimizing production of semiconductor devices on a wafer comprises steps of characterizing at least one effect of at least one manufacturing component on at least one optimization criterion; inputting user optimization data; and, based on the at least o... | 02/19/2008 |
| 7334203 | RaceCheck: a race logic analyzer program for digital integrated circuits Techniques for performing static and dynamic race logic analysis on an integrated circuit (IC) are described herein. According to one aspect of the invention, HDL (hardware description language) design source files of an IC design are compiled into a common design d... | 02/19/2008 |
| 7334200 | Low-error fixed-width modified booth multiplier A low-error fixed-width multiplier receives a W-bit input and produces a W-bit product. In an embodiment, a multiplier (Y) is encoded using modified Booth coding. The encoded multiplier (Y) and a multiplicand (X) are processed together to generate partial products. ... | 02/19/2008 |
| 7334201 | Method and apparatus to measure hardware cost of adding complex instruction extensions to a processor An apparatus, method, and computer-readable media that provide fast and accurate prediction of the hardware cost of logic to extend a processor. Aspects of the invention enable designers to explore instruction set alternatives at the architectural level without comp... | 02/19/2008 |
| 7334037 | Systems and methods for site access Monitoring site access via an intervening control layer within a client is disclosed. In one embodiment of the invention, a computerized system includes a plurality of sites, a monitoring server, and a client. Each site has content referenced be addresses. The monit... | 02/19/2008 |
| 7334052 | Versatile dual port connector element arrangement A hard disk controller (HDC) chip has interchangeable “A” and “B” ports of differential connector element pairs, with one connector element of each pair being disposed closest to the edge of the chip and with the other element inboard of it to facilitate con... | 02/19/2008 |
| 7331025 | Data storage method and data storage device In a data storage method and device, input data having a pattern are divided into a plurality of fields. A first number of rectangles contained in each field of an original image of the pattern is calculated by dividing the field of the original image into one or pl... | 02/12/2008 |
| 7330080 | Ring based impedance control of an output driver One embodiment in accordance with the invention is a method that can include utilizing a ring oscillator module to determine a process corner of an integrated circuit as fabricated that includes the ring oscillator module. The impedance of an output driver of the in... | 02/12/2008 |
| 7331027 | Method for swapping circuits in a metal-only engineering change A method is disclosed for improving design criteria and importantly timing criteria following a metal-only engineering change. The method involves making initial logical changes involving new books (gate-level, filler-cell circuits, called ‘eco books’), running ... | 02/12/2008 |
| 7331030 | Method to unate a design for improved synthesizable domino logic flow A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthes... | 02/12/2008 |
| 7331031 | Method for describing and deploying design platform sets A method for realization of an integrated circuit design including the steps of (i) receiving one or more design platform descriptions and (ii) merging the one or more design platform descriptions into one or more layers of a design flow. The one or more design plat... | 02/12/2008 |
| 7331022 | Method and apparatus for automating pin assignments A method for automating pin assignments through an electronic design automation (EDA) development tool is provided. In the method, components for a chip design are selected and a board in which the chip design is to be implemented is identified. A port of one of the... | 02/12/2008 |
| 7331032 | Computer-aided design system to automate scan synthesis at register-transfer level A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL tes... | 02/12/2008 |
| 7328143 | Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure A method for building a hierarchical representation of a circuit for simulation includes 1) receiving a source file containing SPICE-like netlist descriptions of the circuit in a flattened representation; 2) generating a primitive database using the source file, whe... | 02/05/2008 |
| 7327173 | Delay-locked loop having a pre-shift phase detector A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock ... | 02/05/2008 |
| 7328420 | Circuit design tools with optimization assistance Computer aided design tools are provided that assist circuit designers in optimizing circuit performance. A circuit designer who is designing an integrated circuit may supply circuit design data and constraint data. Computer aided design tools may process the data t... | 02/05/2008 |
| 7328418 | Iso/nested control for soft mask processing This method includes a method for etch processing that allows the bias between isolated and nested structures/features to be adjusted, correcting for a process wherein the isolated structures/features need to be smaller than the nested structures/features and wherei... | 02/05/2008 |
| 7328423 | Method for evaluating logic functions by logic circuits having optimized number of and/or switches A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present inve... | 02/05/2008 |
| 7328329 | Controlling processing of data stream elements using a set of specific function units A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an instruction (cs_ir_s) that is entered in the context of the thread ... | 02/05/2008 |
| 7328413 | Method and circuit for reducing leakage and increasing read stability in a memory device A device and method for increasing the read stability of a memory device includes sizing a sleep transistor according to a size ratio of the transistor relative to a driver transistor forming part of the memory device based on a static noise margin value. A leakage ... | 02/05/2008 |
| 7328416 | Method and system for timing modeling for custom circuit blocks A method is provided for modeling timing characteristics of a circuit block of an integrated circuit, which includes a main circuit and a timing circuit. The method comprises determining an output pin output delay and determining a timing circuit delay. The output p... | 02/05/2008 |
| 7327869 | Computer aided quality assurance software system A software system including simulation routines embedded inside a computer aided drafting (CAD) platform. The routines simulate the inspection processes prior to the execution of the physical inspection process. The simulator works within the host CAD platform and d... | 02/05/2008 |
| 7325220 | Techniques for automatically recommending a suitable programmable IC for a circuit design Techniques are provided for automatically recommending a suitable programmable IC for a circuit design in response to receiving information about the circuit design. The information can be provided in any desired format. For example, specifications defining the circ... | 01/29/2008 |
| 7325219 | Method and apparatus for determining probing locations for a printed circuit board Techniques for automating probing location selection during printed circuit board (PCB) and corresponding PCB tester fixture design are presented. The invention includes a system and algorithm for selecting a probe layout comprising a set of probing locations for a ... | 01/29/2008 |
| 7325232 | Compiler for multiple processor and distributed memory architectures A compiler for multiple processor and distributed memory architectures is described. The compiler uses a high-level language to represent a task-level network of behaviors that describes an embedded system. The compiler maps a plurality of tasks and data onto a mult... | 01/29/2008 |
| 7325209 | Using patterns for high-level modeling and specification of properties for hardware systems This invention is a high-level language to specify electronic system design patterns for functional verification. This invention includes automatic translation of the high-level language specification into assertion code from these patterns and temporal properties f... | 01/29/2008 |
| 7325206 | Electronic design for integrated circuits based process related variations An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjust... | 01/29/2008 |
| 7325213 | Nested design approach A structure for a system of chip packages includes a master substrate and at least one subset substrate of the master substrate. The subset substrate includes a portion of the master substrate that has an identical pin out pattern as the portion of the master substr... | 01/29/2008 |
| 7325221 | Logic system with configurable interface A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration opti... | 01/29/2008 |
| 7324914 | Timing closure for system on a chip using voltage drop based standard delay formats A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one wor... | 01/29/2008 |
| 7325044 | Method for setting up a program-controlled circuit arrangement and circuit arrangement for execution of the method In the case of devices with a program-controlled circuit arrangement operating program instructions are necessary for their operation. In order to reduce the storage space necessary for this, in the case of devices which have a connection to a data transmission netw... | 01/29/2008 |
| 7322019 | Electronic circuit designing method and apparatus, and storage medium An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general layout and wiring information related to devices and wirings included ... | 01/22/2008 |
| 7320642 | Security of gaming software A gaming machine for conducting a wagering game comprises a processing apparatus and a secondary apparatus. To inhibit unauthorized persons from replacing some or all of the software executed by the processing apparatus with unapproved software, the processing appar... | 01/22/2008 |
| 7322016 | Impact checking technique A method includes determining whether or not a statement in a design has any functionality. The functionality includes impact on the operation of the design. Also included in the invention is in impact checker to determine the impact of portions of the design on the... | 01/22/2008 |
| 7320117 | Design method for semiconductor integrated circuit device using path isolation A design method for a semiconductor integrated circuit device wherein for a path having a signal arrival time longer than a desired signal arrival time, and among multiple paths in the semiconductor integrated circuit device, a path isolation is performed so that a ... | 01/15/2008 |
| 7318209 | Pulse-width limited chip clock design A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse wid... | 01/08/2008 |
| 7318150 | System and method to support platform firmware as a trusted process A system and method to support platform firmware as a trusted process. Measurement of a trusted portion of original firmware are measured by a core root of trust measurement (CRTM). The measurement is stored in a secure manner during pre-boot. During operating syste... | 01/08/2008 |
