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| Number | Title | Issue Date |
| 7937673 | Method and system for implementing top down design and verification of an electrical circuit design Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be ... | 05/03/2011 |
| 7917870 | Enhancing a power distribution system in a ceramic integrated circuit package A method, apparatus, and computer program product are disclosed for automatically enhancing a power distribution system (PDS) in a ceramic integrated circuit package. The package includes multiple layers. The entire package is divided into a three-dimensional grid t... | 03/29/2011 |
| 7913193 | Determining relative amount of usage of data retaining device based on potential of charge storing device An integrated circuit and a design structure are disclosed. An integrated circuit may comprise: a data retaining device; a charge storing device coupled to the data retaining device such that a use of the data retaining device triggers a charging of the charge stori... | 03/22/2011 |
| 7908574 | Techniques for use with automated circuit design and simulations Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes genera... | 03/15/2011 |
| 7904838 | Circuits with transient isolation operable in a low power state An integrated circuit includes a core-logic providing a core-logic output, a latch in communication with the core-logic to store a state of the core-logic output, and an isolation circuit for selectively interconnecting the core-logic output to an input of the latch... | 03/08/2011 |
| 7904839 | System and method for controlling access to addressable integrated circuits A circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing one of the addressable c... | 03/08/2011 |
| 7900162 | Read strobe feedback in a memory system A controller circuit is coupled to a memory device over a data/IO bus and a control bus. The controller circuit generates a read enable signal that is transmitted to the memory device to instruct the memory device to drive data onto the data/IO bus. The read enable ... | 03/01/2011 |
| 7895538 | System and method for providing a common instruction table A system includes a storage device including a human readable common instruction table (CIT) stored as a text file. The system also includes CIT access software for performing a method including receiving a request from a first user for all or a subset of the CIT ta... | 02/22/2011 |
| 7890892 | Balanced and bi-directional bit line paths for memory arrays with programmable memory cells Disclosed is a design structure of an improved large scale memory system and, more particularly, an improved memory system that incorporates an array of memory cells that are subjected to minimal location dependent power variations and that, optionally, allows for b... | 02/15/2011 |
| 7890893 | Design structure for semiconductor on-chip repair scheme for negative bias temperature instability Disclosed is a design structure for a semiconductor chip structure that incorporates a localized, on-chip, repair scheme for devices that exhibit performance degradation as a result of negative bias temperature instability (NBTI). The repair scheme utilizes a heatin... | 02/15/2011 |
| 7890891 | Method and apparatus improving gate oxide reliability by controlling accumulated charge A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adap... | 02/15/2011 |
| 7886237 | Method of generating a functional design structure A method in a computer-aided design system for generating a functional design model of a circuit that compensates for changes in resistance of a buried resistor by using a waveform that is representative of the thermal characteristics of the buried resistor. ... | 02/08/2011 |
| 7882455 | Circuit and method using distributed phase change elements for across-chip temperature profiling Disclosed is an across-chip temperature sensing circuit and an associated method that can be used to profile the across-chip temperature gradient. The embodiments incorporate a plurality of phase change elements distributed approximately evenly across the semiconduc... | 02/01/2011 |
| 7882453 | Semiconductor device metal programmable pooling and dies A pool of die designs includes die designs having metal programmable base layers. Die designs from the pool are selected for use in fabricating dies. Die designs are added to the pool by customization of die designs already in the pool or by preparing custom die des... | 02/01/2011 |
| 7882454 | Apparatus and method for improved test controllability and observability of random resistant logic A method for implementing improved observability of random resistant logic included in an integrated circuit (IC) design includes configuring a multiplexer device to pass, to a preexisting storage latch within the design, one of: a signal from one or more observatio... | 02/01/2011 |
| 7882452 | Modeling silicon-on-insulator stress effects A method and system for modeling silicon-on-insulator shallow trench isolation stress effect is described. The method includes creating instance parameters that define dimensions of a body-tie enclosure of gate and gate-end. The instance parameters are added to a ne... | 02/01/2011 |
| 7877709 | Method of placing wires A method of placing wires for placing a shield wire with respect to a shield subject wire placed on a chip, a method includes setting a plurality of wire tracks on the chip, dividing the chip into at least a first area and a second area according to a division bound... | 01/25/2011 |
| 7873921 | Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signal A design structure for an integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply volt... | 01/18/2011 |
| 7873922 | Structure for robust cable connectivity test receiver for high-speed data receiver A design structure embodied in a machine-readable medium used in a design process may include a system for detecting a fault in a signal transmission path. Such system may include, for example, a hysteresis comparator including a latch having n-type field effect tra... | 01/18/2011 |
| 7870513 | Application-specific integrated circuit equivalents of programmable logic and associated methods Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA lo... | 01/11/2011 |
| 7870514 | Method of designing a pattern A method of designing a pattern of a hole pattern having a configuration, in which grid of interval smaller than a minimum permissible pitch according to a design rule for a semiconductor integrated circuit is provided in a pattern drawing, a hole pattern is arrange... | 01/11/2011 |
| 7865847 | Method and system for creating and programming an adaptive computing engine A system and corresponding method for creating an adaptive computing engine (ACE) includes algorithmic elements, ACE building blocks, and creates a design for heterogeneous nodes to provide appropriate hardware circuit functions that implement the algorithmic elemen... | 01/04/2011 |
| 7861193 | Reuse of circuit labels for verification of circuit recognition A method for identifying instances of a smaller circuit in a larger circuit is provided. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and ... | 12/28/2010 |
| 7861191 | Method and apparatus for characterizing signals Methods and corresponding computer systems for characterizing signals and applications thereof are provided that use a functional depending on signal waveforms. ... | 12/28/2010 |
| 7861190 | Power-driven timing analysis and placement for programmable logic An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided ... | 12/28/2010 |
| 7861192 | Technique to implement clock-gating using a common enable for a plurality of storage cells A system and method for providing clock gating while reducing area and power on an integrated circuit (IC) chip. An array of registers or memory cells may have a single clock gating circuit, rather than multiple circuits such as one clock gating circuit for each bit... | 12/28/2010 |
| 7853901 | Unified layer stack architecture A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the ... | 12/14/2010 |
| 7844922 | Semiconductor integrated circuit device and design method thereof In a semiconductor integrated circuit device in which dynamic type logic circuit cells, in which transistors constituting a logic section are in an unconnected condition, are arranged in two-dimensional array form and wiring for distributing a clock signal to each r... | 11/30/2010 |
| 7844923 | Semiconductor integrated circuit designing method, semiconductor integrated circuit device, and electronic device A simple method for designing a semiconductor integrated circuit having the ZSCCMOS structure is provided. For each kind of primitive logic gate, a logic gate cell H and a layout cell H each having a high-potential power supply end connected to VDD and a ... | 11/30/2010 |
| 7840916 | Structure for on-chip electromigration monitoring system A design structure embodied in a machine readable medium used in a design process can include apparatus of a semiconductor chip operable to detect an increase in resistance of a monitored element of the semiconductor chip. The design structure can include, for examp... | 11/23/2010 |
| 7840915 | Methods and media for forming a bound network Methods and media for forming a bound network are provided. In some embodiments, methods for forming a bound network include: decomposing an asynchronous input network to form a network of base functions, wherein the network of base functions includes simple base fu... | 11/23/2010 |
| 7840913 | Restricting state diagrams with a set of predefined requirements to restrict a state diagram to a state diagram of a moore or mealy machine The present invention provides a user of a state diagramming environment with the ability to specify if the user wants to develop a Moore machine or a Mealy machine. To achieve this, a set of predefined requirements is provided that restricts the state diagram seman... | 11/23/2010 |
| 7840914 | Distributing computations in a parallel processing environment A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises accepting a set of instructions corresponding to a portion of a program that performs a computation repeatedly; identifyin... | 11/23/2010 |
| 7840917 | Method of correcting a design pattern for an integrated circuit and an apparatus for performing the same In an apparatus and method for automatically correcting a design pattern in view of different process defects, defect characteristic functions that indicate frequencies of each process defect independent from one another are generated, and a normalization factor tha... | 11/23/2010 |
| 7831935 | Method and architecture for power management of an electronic device A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional cir... | 11/09/2010 |
| 7831936 | Structure for a system for controlling access to addressable integrated circuits A design structure for a circuitry access system for controlling access to addressable circuit elements of an integrated circuit. The circuitry access system includes a first storage element having a first listing of unique identifiers each identifier representing o... | 11/09/2010 |
| 7823091 | Compilable, reconfigurable network processor A processor, particularly a network processor, is designed by first writing code to be processed by the processor. That code is then electronically compiled to design hardware of the processor and to provide executable code for execution on the designed hardware. To... | 10/26/2010 |
| 7823092 | Method and apparatus for implementing a parameterizable filter block with an electronic design automation tool An electric design automation (EDA) tool for generating a design of a system on a field programmable gate array (FPGA) includes a graphical user interface to create a block based schematic. The EDA tool includes a library that includes a parameterizable filter block... | 10/26/2010 |
| 7814442 | Resettable memory apparatuses and design Resettable memory implemented using memory without reset and methods and apparatuses to design the same. A resettable memory may include: a plurality of resettable memory cells; a plurality of memory units; and a reset information propagation logic coupled to the re... | 10/12/2010 |
| 7814441 | System and method for identifying original design intents using 3D scan data Programmatic extraction and management of solid and surface modeling parameters from raw 3D scan data is discussed. An automated process reads raw 3D scan data and works in communication with a CAD system able to perform CAD part modeling. The user is provided with ... | 10/12/2010 |
