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"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 7747936 | Device for protection against error injection into an asynchronous logic block of an elementary logic module A logic circuit comprises a logic module comprising a functional logic block supplying a functional result, and a functional flip-flop receiving the functional result and supplying a synchronous result. A module for checking the functional logic block comprises a ch... | 06/29/2010 |
| 7624336 | Selection of status data from synchronous redundant devices Techniques are provided for selecting status data. Redundant views are obtained from multiple synchronous redundant devices. It is determined that the redundant views from the multiple synchronous redundant devices are conflicting. A redundant view score is calculat... | 11/24/2009 |
| 7546518 | Received data compensating device Provided is a compensating device for a received data can be used in a wide application by a single apparatus for various wiring configurations and transmission media. The compensating device provided between a receiver circuit in a physical layer and a processing d... | 06/09/2009 |
| 7512873 | Parallel processing apparatus dynamically switching over circuit configuration A parallel processing apparatus dynamically switching over a circuit configuration includes a plurality of computing elements, a network establishing connections between the plural computing elements, a plurality of selectors provided corresponding to the plurality ... | 03/31/2009 |
| 7434128 | Systems and methods for identifying system links In one embodiment, a method for identifying links in a system under evaluation includes assigning unique identifiers to drivers of the system, emitting the identifiers from the drivers on associated links, collecting data received by receivers of the system, and com... | 10/07/2008 |
| 7428694 | Device for protection against error injection into a synchronous flip-flop of an elementary logic module A logic circuit comprises a logic module comprising a functional synchronous flip-flop receiving a functional result comprising several bits in parallel, and supplying a synchronous result. A module for checking the integrity of the functional flip-flop comprises a ... | 09/23/2008 |
| 7426684 | Lost-cycle measurement using cycle counter A method of lost-cycle measurement using a cycle counter. In some embodiments, the lost-cycle measurement method comprises: getting a current cycle counter value; finding a number of elapsed cycles between the current cycle counter value and a preceding cycle counte... | 09/16/2008 |
| 7395483 | Method and apparatus for performing error-detection and error-correction One embodiment of the present invention provides a system that facilitates detecting and correcting errors. The system operates by receiving a data packet comprised of p words on a communication pathway, wherein each bit of a word is received on a separate data line... | 07/01/2008 |
| 7370257 | Test vehicle data analysis A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix for... | 05/06/2008 |
| 7366172 | Receiver-driven layered error correction multicast over heterogeneous packet networks A system and method for correcting errors and losses occurring during a receiver-driven layered multicast (RLM) of real-time media over a heterogeneous packet network such as the Internet. This is accomplished by augmenting RLM with one or more layers of error corre... | 04/29/2008 |
| 7363546 | Latent fault detector A latent error detector may be configured to reveal latent errors within a plurality of components within a computer system. The latent error detector may be configured to access configuration data specifying one or more types of components and one or more modules f... | 04/22/2008 |
| 7359980 | Progressive streaming media rendering A system and process for providing progressively higher quality versions of an audio and/or video program over a client-server based network. In response to a user command to view a particular program, the client requests layered data associated with the program fro... | 04/15/2008 |
| 7360118 | Method and system for verifying data in a shadow memory A system for verifying data in a shadow memory is provided that includes a main memory, a shadow memory, a shadow memory initializer, and a shadow memory verifier. The main memory is operable to store main data persistently. The shadow memory is operable to store sh... | 04/15/2008 |
| 7337356 | Systematic and random error detection and recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e... | 02/26/2008 |
| 7321612 | Bit stream conditioning circuit having adjustable PLL bandwidth A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side... | 01/22/2008 |
| 7318169 | Fault tolerant computer A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long in... | 01/08/2008 |
| 7317769 | Bit stream conditioning circuit having adjustable input sensitivity A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side... | 01/08/2008 |
| 7313741 | Integrated semiconductor memory An integrated semiconductor memory includes memory cells that store a first data record has at least one datum with a first or second data value and a second data record has at least one datum with the first or second data value. The integrated semiconductor memory ... | 12/25/2007 |
| 7310761 | Apparatus and method for retransmitting data packets in mobile ad hoc network environment A method and an apparatus for requesting packet redelivery in a mobile ad hoc network environment. The method includes receiving a first packet periodically broadcasted, extracting packet delivery information of a second packet from the first packet, the second pack... | 12/18/2007 |
| 7296106 | Centerplaneless computer system A computer system which may allow a centerplaneless design. The computer system may include various client circuit boards including processor circuit boards, memory circuit boards and switch circuit boards. The processor circuit boards may each include at least one ... | 11/13/2007 |
| 7296082 | Method and system for fault tolerant media streaming over the internet A replication process to provide fault tolerance for a streaming signal in a computer network. In one embodiment, the original or source signal is sent to several splitters which, in turn, each make copies of the signal and send the copies into a second layer of dev... | 11/13/2007 |
| 7278071 | Receiving circuit for receiving message signals The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the... | 10/02/2007 |
| 7259602 | Method and apparatus for implementing fault tolerant phase locked loop (PLL) A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes a divide by N circuit defined by a plurality of sub-divide by N functions, each providing a feedback frequency signal applied to a voter circuit. ... | 08/21/2007 |
| 7260742 | SEU and SEFI fault tolerant computer A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run add... | 08/21/2007 |
| 7251550 | Aircraft accessory monitor Methods and apparatus are provided for monitoring an aircraft accessory. The apparatus comprises a processor associated with said aircraft accessory, a transducer coupled to said processor and operable to produce parametric data relating to said aircraft accessory a... | 07/31/2007 |
| 7249306 | System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage de... | 07/24/2007 |
| 7237032 | Progressive streaming media rendering A system and process for providing progressively higher quality versions of an audio and/or video program over a client-server based network. In response to a user command to view a particular program, the client requests layered data associated with the program fro... | 06/26/2007 |
| 7237213 | Process and device for timing analysis of a circuit Circuit elements are operated as a function of a state of at least one change-over signal, in each case with a particular respective clock mode. Timing analysis is carried out by means of a description of the circuit. The description contains information as to wheth... | 06/26/2007 |
| 7237148 | Functional interrupt mitigation for fault tolerant computer A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or ci... | 06/26/2007 |
| 7237149 | Method and apparatus for qualifying debug operation using source information A data processing system (10) has a system debug module (19) coupled to a processor (12) for performing system debug functions. Located within the system, and preferably within the processor, is debug circuitry (32) that selectively provi... | 06/26/2007 |
| 7185261 | Multidimensional turbo product code decoding of encoded data transmitted over diversity channel A system and method to transmit and receive forward error corrected data in a diversity communications system is provided. Using diversity techniques, multiple copies of the transmitted data are received with varying degrees of corruption due to channel impairments.... | 02/27/2007 |
| 7168019 | Method and module for universal test of communication ports The present invention relates to a method and an universal module for testing functions of communication ports of a computer, including both parallel port and serial port. The module includes a logic control unit and connects to a communication port (a serial or a p... | 01/23/2007 |
| 7162557 | Competition arbitration system A competition arbitration system in which chances for using a resource of a computer such as a bus or the like among devices are fair is provided. Pulses are sequentially generated periodically from a pulse generating circuit. It is assumed that first device outputt... | 01/09/2007 |
| 7152192 | System and method of testing a plurality of memory blocks of an integrated circuit in parallel A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits havi... | 12/19/2006 |
| 7139344 | Method and apparatus for effecting synchronous pulse generation for use in variable speed serial communications A method for effecting synchronous pulse generation for use in variable speed serial communications is provided. The method includes the steps of obtaining a communication link speed; generating a difference signal representing a signal level difference between at l... | 11/21/2006 |
| 7127669 | Redundant path communication methods and systems The systems and methods described herein provide a redundant communication path. The systems and methods can provide a second source for the same data under many circumstances. These circumstances can include, for example, 1) when data incurs errors during transmiss... | 10/24/2006 |
| 7117423 | Methods and systems for multiple substream unequal error protection and error concealment Methods and systems for streaming data in a network. Whether the network is experiencing high packet loss may be determined by a rate control module. If high packet loss is experienced, data is encoded into multiple streams by a coder using temporal domain partition... | 10/03/2006 |
| 7103125 | Method and apparatus for effecting synchronous pulse generation for use in serial communications A method for effecting synchronous pulse generation for use in serial communications is provided. The method includes the steps of generating a difference signal representing a signal level difference between at least two data stream signals; providing a clock signa... | 09/05/2006 |
| 7100078 | Method and apparatus for restoration of lost blocks in a multicast data transmission Reliable multicast communication is provided by sending data from a transmitting device to receiving devices as “bursts” of data transfer units. Each receiving device provides status describing which data transfer units within each previously transmitted burst r... | 08/29/2006 |
| 7068304 | Apparatus for assessing quality of a picture in transmission, and apparatus for remote monitoring quality of a picture in transmission In a transmission chain having series-connected a TSC unit, an encoder, a transmission path, a decoder, and an up-converter, characteristic value extracting units are connected to input/output points A, B, C, and D of these transmission processing units respectively... | 06/27/2006 |
