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| Number | Title | Issue Date |
| 8099659 | Logic tester and method for simultaneously measuring delay periods of multiple tested devices The invention provides a logic tester. In one embodiment, the logic tester is coupled to a plurality of tested devices, and includes a function generator and a pattern comparator. The function generator generates an initial code sequence as an input signal of the te... | 01/17/2012 |
| 8078950 | Delay measuring device and semiconductor device A delay measuring device according to the present invention comprises a memory cell, a delay element and a selector. The memory cell is provided with a non-inversion output terminal and an inversion output terminal, and the memory cell fetches a data value inputted ... | 12/13/2011 |
| 7900129 | Encoded mechanism for source synchronous strobe lockout An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed ve... | 03/01/2011 |
| 7562285 | Unidirectional error code transfer for a bidirectional data link A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a por... | 07/14/2009 |
| 7444565 | Re-programmable COMSEC module A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output fro... | 10/28/2008 |
| 7437629 | Method for checking the refresh function of an information memory A method for checking the refresh function of a memory having a refresh device includes the steps of, first, ascertaining whether or not refresh request pulses are being produced on the information memory and, if so, at what intervals of time from one another these ... | 10/14/2008 |
| 7392465 | Testing ram address decoder for resistive open defects Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types o... | 06/24/2008 |
| 7379395 | Precise time measurement apparatus and method A time measurement system that uses two signals generated by direct digital synthesis. The generated signals have the same frequency but different phase. One signal is used to identify the start of the measurement interval and the other signal is used to identify a ... | 05/27/2008 |
| 7363556 | Testing apparatus and testing method A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail... | 04/22/2008 |
| 7330993 | Slew rate control mechanism According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate base... | 02/12/2008 |
| 7324558 | Method and apparatus for controlling the timing of a communication device A system timer controls the timing at which a mobile communication device communicates with a base station. The system timer includes a sequencer that executes a set of instructions stored in a sequencer RAM thereby causing a set of control signals to be supplied to... | 01/29/2008 |
| 7324932 | Virtual test environment A method of and an apparatus for designing a test environment providing reliable test signal integrity, and of evaluating performance of the test environment and an electronic device during testing of the electronic device. A virtual test environment is created emul... | 01/29/2008 |
| 7292044 | Integrating time measurement circuit for a channel of a test card In a first embodiment of the invention there is provided an electronic chip for use with an automatic testing equipment device testing a device under test. The device under test has a plurality of pins and the electronic chip is placed in a channel of a test card th... | 11/06/2007 |
| 7287198 | Method for monitoring a microprocessor and circuit arrangement having a microprocessor A method for monitoring a microprocessor and a circuit arrangement having a microprocessor are described. A microprocessor is monitored using an assigned watchdog. The watchdog monitors whether reset pulses are received within a time interval of predetermined durati... | 10/23/2007 |
| 7272646 | Network monitor internals description A method and apparatus for a network monitor internals mechanism that serves to translate packet data into multiple concurrent streams of network event data is provided. The data translation is accomplished by interpreting both sides of each protocol transaction. | 09/18/2007 |
| 7269524 | Delay lock loop delay adjusting method and apparatus Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is the... | 09/11/2007 |
| 7249203 | Programmatic time-gap defect detection apparatus and method Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the pro... | 07/24/2007 |
| 7240248 | Apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the... | 07/03/2007 |
| 7240269 | Timing generator and semiconductor testing device A timing generator f or a semiconductor test device reduces pattern-dependent jitters and timing errors of timing pulse signals. In the timing generator, a delaying circuit (variable delaying means, clock signal delaying circuit) is disposed on an input terminal sid... | 07/03/2007 |
| 7234092 | Variable clocked scan test circuitry and method A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift c... | 06/19/2007 |
| 7225362 | Ensuring the health and availability of web applications A web server arrangement is provided having a kernel-mode listener service capable of receiving web requests and providing the web requests to at least one user mode web application. The listener service and the web application are operatively configured by a user-m... | 05/29/2007 |
| 7219270 | Device and method for using a lessened load to measure signal skew at the output of an integrated circuit A device and method are provided for testing the timing of an output signal from a circuit. The output signal can be sent from a circuit contained within a portion of an integrated circuit, and represents a response to a test pattern or stimuli applied to that circu... | 05/15/2007 |
| 7183829 | Semiconductor device including a plurality of circuit blocks provided on a chip and having different functions A logic circuit block and a memory circuit block are provided on a semiconductor chip. A timing adjustment circuit block for adjusting the propagation timing of signals is provided on a line between the circuit blocks. A timing adjustment circuit unit includes: a de... | 02/27/2007 |
| 7171611 | Apparatus for determining the access time and/or the minimally allowable cycle time of a memory An apparatus for determining the access time and the minimally allowable cycle time of a memory, comprising a clock for generating a signal which stimulates memory data output, programmable delay means for generating a delayed signal, sample-and-hold means for sampl... | 01/30/2007 |
| 7137036 | Microcontroller having an error detector detecting errors in itself as well A microcontroller including a CPU (Central Processor Unit) is capable of detecting the error of its structural part. The CPU executes a first initialization phase in response to a power-on reset signal output from a power-on reset circuit, then executes a second ini... | 11/14/2006 |
| 7117513 | Apparatus and method for detecting and correcting a corrupted broadcast time code An apparatus and method for processing audience measurement data detects and corrects one or more corrupted time codes. The corrupted time codes are identified by calculating a first set of intervals between a set of read times that may, but need not, be consecutive... | 10/03/2006 |
| 7100067 | Data transmission error reduction via automatic data sampling timing adjustment A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of ti... | 08/29/2006 |
| 7096104 | Control unit for a load Control unit for a load, in particular for a sliding sunroof control of a vehicle, having a microprocessor and having an integrated voltage regulator for generating the supply voltage of the microprocessor from the battery voltage of an on-board battery, in which ca... | 08/22/2006 |
| 7092827 | Edge placement accuracy of signals generated by test equipment A software controlled mechanism causing a test equipment to place the edges of test signals accurately. The mechanism determines expected time of occurrence of an edge of a signal in relation to a tester cycle time. The mechanism sends commands to the test equipment... | 08/15/2006 |
| 7076697 | Method and apparatus for monitoring component latency drifts A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such a... | 07/11/2006 |
| 7075336 | Method for distributing clock signals to flip-flop circuits A method for distributing clocks to flip-flop circuits which constitute a logic circuit includes obtaining a timing slack of a first minimum delay time with respect to a minimum delay constraint time and a timing slack of a first maximum delay time with respect to a... | 07/11/2006 |
| 7065693 | Implementation of test patterns in automated test equipment An improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern. In the present invention, a timed test pattern is controlled by a timing generator operable to change the timing... | 06/20/2006 |
| 7058909 | Method of generating an efficient stuck-at fault and transition delay fault truncated scan test pattern for an integrated circuit design A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-... | 06/06/2006 |
| 7042909 | Method and apparatus for controlling the timing of a communication device A system timer for controlling the timing at which a communication device communications. The system timer can include a memory device and a processor. The memory device can be adapted to store a set of software instructions which can be executed by the processor in... | 05/09/2006 |
| 7043709 | Method and apparatus for determining gate-level delays in an integrated circuit A system is provided for determining voltage at the output of a gate in an integrated circuit. The system locates a gate within the integrated circuit and looks up a set of output current waveforms as a function of time for different effective capacitances at the ga... | 05/09/2006 |
| 7016443 | Synchronization method and system for clock signal sources, in particular in packet transmission communication systems The invention relates to a method for synchronization of clock sources in a communications system, in particular a radio communications system, having a large number of devices (PSTN, MSC, RNM, BSi, MSi, OMC) which communicate directly or indirectly with one another... | 03/21/2006 |
| 7010724 | Operating system hang detection and methods for handling hang conditions Circuitry for detecting operating system hang conditions is provided. The circuitry includes interrupt logic for receiving system interrupts targeted for a central processing unit. Further included is hang detection logic that is in communication with the interrupt ... | 03/07/2006 |
| 6998892 | Method and apparatus for accommodating delay variations among multiple signals A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines between different levels are detected. The timing of a signal affecting re... | 02/14/2006 |
| 6961879 | Apparatus and method for counting error rates in an optical compact disc storage system A method and system are disclosed for counting error rates occurring within an optical compact disk system as data is read from an optically encoded compact disk. In a preferred embodiment error flag data are generated as errors occur within the optical compact disk... | 11/01/2005 |
| 6948103 | Watchdog timer and method for detecting abnormal operation of computer, and computer including the timer A counter counts pulses of a clock generated by an oscillator. A control register clears the counted value, in response to a reset signal sent from an external circuit. In the case where the counted value exceeds a limit value, an output control circuit outputs a re... | 09/20/2005 |
