Famous Patents
William F. Semple, a dentist, was awarded the first US Patent on chewing gum in 1869. His recipe contained powdered chalk.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8185812 | Single event upset error detection within an integrated circuit An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These s... | 05/22/2012 |
| 8161366 | Finite state machine error recovery A method and system for using a magnitude comparator circuit and a flag bit, for detecting and preventing errors from occurring in the FSM state bits that could otherwise cause the system to hang. Preferably, the flag bit is set with all the valid state transitions,... | 04/17/2012 |
| 8060814 | Error recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e... | 11/15/2011 |
| 7707484 | Test apparatus and test method with features of adjusting phase difference between data and reference clock and acquiring adjusted data The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires th... | 04/27/2010 |
| 7689897 | Method and device for high speed testing of an integrated circuit An integrated circuit and a method for testing an integrated circuit. The method includes providing a first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence; characterized by receiving, by a first me... | 03/30/2010 |
| 7627807 | Monitoring a data processor to detect abnormal operation Monitoring logic 20 for monitoring a data processor 10 to detect if it is not operating as anticipated, the monitoring logic 20 comprising: a timer 27 operable to measure a predetermined time; detection logic 24; and control logic ... | 12/01/2009 |
| 7536632 | Method for monitoring data processing system availability A method for monitoring the availability of a data processing system is proposed. For example, the system runs a management application, which involves the periodic transmission of blocks of data from multiple local computers to a central computer. In the method of ... | 05/19/2009 |
| 7512872 | Test apparatus and test method The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires th... | 03/31/2009 |
| 7464325 | Information terminal device Detection as to the reproduction expiration time of contents is executed, using the measured time of a system clock managed based on system time data from a base station BS. If the reproduction expiration time of the contents is not exceeded, the contents can be rep... | 12/09/2008 |
| 7403866 | High-resolution, timer-efficient sliding window Detection of whether more than a number N of events have occurred within a duration of time defined by a sliding time window includes performing an event detection procedure in response to each occurrence of an event. The event detection procedure includes associati... | 07/22/2008 |
| 7400178 | Data output clock selection circuit for quad-data rate interface A method for selecting a data output clock signal includes providing a complementary output clock signal pair to a combinational logic circuit, thereby generating a reset control signal. The reset control signal is activated if the complementary output clock signals... | 07/15/2008 |
| 7392465 | Testing ram address decoder for resistive open defects Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types o... | 06/24/2008 |
| 7366086 | Crosstalk reduction in a backplane employing low-skew clock distribution A system for a backplane that employs i) an adjustment of positive-to-negative (P-N) driver skew of a transmit signal of a relatively high-speed differential driver to reduce far-end crosstalk, ii) a high-speed differential subtraction circuit combining a gain-adjus... | 04/29/2008 |
| 7363556 | Testing apparatus and testing method A testing apparatus for testing a memory-under-test includes a writing section for writing preset test data into each page of said memory-under-test to test said memory-under-test and a fail memory unit for storing the test result of said memory-under-test. The fail... | 04/22/2008 |
| 7363546 | Latent fault detector A latent error detector may be configured to reveal latent errors within a plurality of components within a computer system. The latent error detector may be configured to access configuration data specifying one or more types of components and one or more modules f... | 04/22/2008 |
| 7355384 | Apparatus, method, and computer program product for monitoring and controlling a microcomputer using a single existing pin A method, apparatus, and computer program product are disclosed for monitoring and controlling a device using only one input/output (I/O) communication pin of the device. The pin is configured to be used to both transmit and receive data. Logical ones are generated ... | 04/08/2008 |
| 7355387 | System and method for testing integrated circuit timing margins An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit includes circuitry for testing the timing margins of memory devices by determining the re... | 04/08/2008 |
| 7356109 | Apparatus for and method of measuring clock skew Timing jitter sequences Δφj[n] and Δφk[n] of respective clock signals under measurement xj(t) and xk(t) are estimated, and a timing difference sequence between those timing jitter sequences is calculated. In addition, ... | 04/08/2008 |
| 7355936 | Disc recording medium, disc drive apparatus, and reproduction method First data representing user data and third data use the same error correction codes. The first data has a first error correction block structure and the third data has a second error correction block structure. That is to say, the first data and the third data have... | 04/08/2008 |
| 7349506 | Semiconductor integrated circuit and method for testing the same A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmissio... | 03/25/2008 |
| 7340629 | Method and system for application-based normalization of processor clocks in a multiprocessor environment A method is presented for enabling application-level software to normalize processor clock values within a multiprocessor data processing system. A first processor number associated with a first processor is obtained such that the first processor executes one or mor... | 03/04/2008 |
| 7340024 | Parallel fractional interpolator with data-rate clock synchronization A circuit for single or parallel digital fractional interpolation of data samples has a fractional interpolator filter, an oscillator for outputting timing signals to the fractional interpolator filter, and a detector loop with a strobe feedback from the oscillator ... | 03/04/2008 |
| 7336750 | Optimal one-shot phase and frequency estimation for timing acquisition A method and system for an optimal one-shot estimate of phase and frequency for timing acquisition employ a maximum a posteriori (MAP) formulation to calculate a cost function that is a function of an estimated frequency and an estimated phase. A plurality of cost f... | 02/26/2008 |
| 7336572 | Detecting sync patterns for optical media A sync finder module for an optical medium playback device that generates a bit stream including sync patterns and data blocks comprises a pulse jitter detect module that receives the sync pattern, which includes a plurality of transitions each having a desired posi... | 02/26/2008 |
| 7334014 | Consistent time service for fault-tolerant distributed systems A consistent time service that provides a method of maintaining deterministic clock-related operations for a group of replicas in a fault-tolerant distributed system. A consistent clock synchronization algorithm is utilized that yields a single consistent group cloc... | 02/19/2008 |
| 7330993 | Slew rate control mechanism According to one embodiment a computer system is disclosed. The computer system includes a bus and a chipset coupled to the bus. The chipset detects the slew rate of a signal transmitted over the bus by the chipset. In addition the chipset adjusts the slew rate base... | 02/12/2008 |
| 7327818 | Sync pattern detection method and apparatus A sync pattern detection apparatus includes a sync pattern detection unit configured to detect a sync pattern from an input signal, a plurality of sync pattern protection units configured to protect the sync pattern detected by the sync pattern detection unit, a rel... | 02/05/2008 |
| 7328381 | Testing system and method for memory modules having a memory hub architecture A testing method and system is used to test memory modules each of which has a memory hub coupled to a plurality of memory devices. The testing system and method includes a test interface circuit having a memory interface that is coupled to transmit and receive memo... | 02/05/2008 |
| 7321978 | Overclock detection An overclock detector may define a plurality of detection periods based upon a reference clock signal. Further, the overclock detector may activate an overclock response in response to determining an operating clock signal generating too many cycles in each of a plu... | 01/22/2008 |
| 7319340 | Integrated circuit load board and method having on-board test circuit An integrated circuit load board includes a substrate on which a plurality of integrated circuit sockets and an integrated test circuit are mounted. The integrated test circuit generates test signals that are applied to the integrated circuit sockets. The integrated... | 01/15/2008 |
| 7313753 | Detector for detecting information carried by a signal having a sawtooth-like shape A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a first band-pass filter with center frequency around a first frequency value for filtering the signal and generating a first filtered signal, a second band-... | 12/25/2007 |
| 7310283 | Apparatus and method for controlling clock signal in semiconductor memory device An operation clock controller for preventing a semiconductor memory device from operating when an operation frequency of an external clock is higher than a predetermined frequency. The operation clock controller includes a clock buffer for buffering an external cloc... | 12/18/2007 |
| 7296203 | Test apparatus, program and recording medium There is provided a test apparatus for testing a device-under-test, having a master channel provided in correspondence to one of output pins of the device-under-test to sample an output signal of the corresponding output pin and a slave channel provided in correspon... | 11/13/2007 |
| 7296170 | Clock controller with clock source fail-safe logic A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast in... | 11/13/2007 |
| 7292513 | Method of correcting clock of compact disk and circuit thereof A circuit for correcting a clock of a compact signal and a method therefor. The method comprises: receiving a data signal and a clock signal; and generating a sync pattern signal by using the clock signal to check the data signal. Then, a detection window signal acc... | 11/06/2007 |
| 7290249 | System and method for java message service mark-up language A system and method for Java Message Service Mark-up Language (JMSML). The system includes an extensible engine that performs the task of parsing input data and converting it to Java JMS/JMX API, and then executes the JMSML program. ... | 10/30/2007 |
| 7286452 | Apparatus and method for detecting synchronization of address in pre-groove for optical storage device An apparatus and method detecting synchronization of address in pre-groove (ADIP), allowing an optical storage device to write data to an accurate location of a disc includes a bit synchronization detecting unit and a word synchronization detecting unit. The bit syn... | 10/23/2007 |
| 7283070 | Dynamic calibration of I/O power supply level An input/output interface is used to transmit data between a transmitting circuit and a receiving circuit. Selectively during both system startup and system operation, a known bit pattern transmitted by the transmitting circuit is compared to a received bit pattern.... | 10/16/2007 |
| 7284169 | System and method for testing write strobe timing margins in memory devices Write strobe preamble/postamble test circuitry includes a test signal generator generating first and second digital signals. Also included are a pair of phase interpolators for varying the transition times of respective transmitter clock signals. When enabled, a tra... | 10/16/2007 |
| 7278071 | Receiving circuit for receiving message signals The invention relates to a receiving circuit for receiving message signals, having a sampler for converting the message signal into a sampled signal, an analyzing unit for decoding the sampled signal and checking it for errors, and a control unit for controlling the... | 10/02/2007 |
