Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
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| Number | Title | Issue Date |
| 8190982 | Error-tolerant multi-threaded memory systems with reduced error accumulation Systems and methods establishing and/or utilizing an error-tolerant multithreaded register file are provided. The systems and methods employ dynamic multithreading redundancy (DMR) for error correction. Non-overlapped register access patterns associated create hardw... | 05/29/2012 |
| 8176404 | Systems and methods for stepped data retry in a storage system Various embodiments of the present invention provide systems and methods for data processing retries. As an example, a data processing retry circuit is discussed that includes a stepped erasure window register, and an erasure flag set circuit. The stepped erasure wi... | 05/08/2012 |
| 8171385 | Load balancing service for servers of a web farm A system for maximizing the efficiency of a load balancing server for an asymmetric web farm utilizes a TCP stack and data packets to send and receive client service requests. An internal buffer enables each web server in the web farm to balance their loading based ... | 05/01/2012 |
| 8112700 | Nanoscale interconnection interface One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals inp... | 02/07/2012 |
| 8095861 | Cache function overloading A method includes checking a first parameter that indicates whether parity generation and checking for a at least a sub-portion of a cache line is disabled, setting at least one parity bit, corresponding to the sub-portion, in the cache line with a second parameter ... | 01/10/2012 |
| 7987384 | Method, system, and computer program product for handling errors in a cache without processor core recovery A method for handling errors in a cache memory without processor core recovery includes receiving a fetch request for data from a processor and simultaneously transmitting fetched data and a parity matching the parity of the fetched data to the processor. The fetche... | 07/26/2011 |
| 7954042 | Check testing of an address decoder For checking an address decoder of a data memory, from a record of addresses of the data memory, designated as base addresses, one after another each base address is selected, and the following steps are executed for the respectively selected base address: ... | 05/31/2011 |
| RE42228 | Method and apparatus for using data protection code for data integrity in on-chip memory Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along ... | 03/15/2011 |
| 7844888 | Electronic device, method for operating an electronic device, memory circuit and method of operating a memory circuit The present invention relates to a method of operating an electronic device and an electronic device. The electronic device comprises a signal path for transmitting data, an input/output interface connected with the signal path, a masking circuit and an error calcul... | 11/30/2010 |
| 7761780 | Method, apparatus, and system for protecting memory A parity adder obtains a second data by adding a parity for first data to be written to a memory to the first data. An access-key register holds an access key unique to a source of request. A first operating unit obtains a third data by calculating an XOR between th... | 07/20/2010 |
| 7761779 | Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a ... | 07/20/2010 |
| 7603614 | Method and system for indicating an executable as trojan horse A method and system for indicating an executable as Trojan Horse, based on the CRC values of the routines of an executable. The method comprising a preliminary stage in which the CRC values of the routines of known Trojan Horses are gathered in a database, and a sta... | 10/13/2009 |
| 7581163 | Detection of corrupted memory pointers within a packet-processing device Techniques are described for detecting corruption of buffer pointers passed between a local processor and a remote processor on a network device. For example, the first processor, which may be a memory controller, receives and stores packets within memory. A second ... | 08/25/2009 |
| 7559009 | System and method for performing parity checks in disk storage systems A cyclic redundancy check (CRC) system for a storage controller comprises a memory that stores first sector data and a corresponding CRC non-zero seed value. A buffer control module includes a CRC module, calculates a CRC value of the first sector data with the CRC ... | 07/07/2009 |
| 7451387 | Autonomous method and apparatus for mitigating soft-errors in integrated circuit memory storage devices at run-time Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity e... | 11/11/2008 |
| 7428693 | Error-detecting encoding and decoding apparatus and dividing apparatus Disclosed are an error-detecting encoding apparatus for creating parity bits by error-detecting encoding processing, appending the parity bits to an input data string and encoding the data string, and an error-detecting decoding apparatus for detecting error using t... | 09/23/2008 |
| 7424662 | Method and system for providing low density parity check (LDPC) encoding An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The informati... | 09/09/2008 |
| 7415633 | Method and apparatus for preventing and recovering from TLB corruption by soft error A detection and recovery mechanism is herein disclosed for soft errors corrupting TLB data. The mechanism works with a hardware page walker (HPW) and instruction steering control mechanisms in a processor to provide soft error recovery in the TLB arrays and latches.... | 08/19/2008 |
| 7395462 | Defect estimation apparatus and related method A weighted defect estimating apparatus and a related method for determining a defect estimation value are disclosed. The weighted defect detecting apparatus includes: a defect detecting unit for generating a defect value when a defect in a predetermined region of an... | 07/01/2008 |
| 7380200 | Soft error detection and correction by 2-dimensional parity The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity... | 05/27/2008 |
| 7380179 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurali... | 05/27/2008 |
| 7370138 | Mobile communication terminal including NAND flash memory and method for booting the same A mobile communication terminal with a NAND flash memory is described. The terminal includes a memory for storing address information indicative of a start address of a specific area including boot data to be read from the NAND flash memory; and a sub-controller for... | 05/06/2008 |
| 7370230 | Methods and structure for error correction in a processor pipeline Methods and structures for an improved processor pipeline to eliminate the effect of correctable soft errors on processor/memory pipeline performance. Features and aspects hereof provide that the pipeline is extended by the addition of one or more information correc... | 05/06/2008 |
| 7353423 | System and method for improving the performance of operations requiring parity reads in a storage array system A system for improving a performance of a write process in an exemplary RAID system reduces a number of IOs required for a short write in a RAID algorithm by using a replicated-parity drive. Parity is stored on the parity portion of the disk drives. A replicated-par... | 04/01/2008 |
| 7353448 | Methods, architectures, circuits and systems for transmission error determination Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding ... | 04/01/2008 |
| 7353438 | Transparent error correcting memory A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory ... | 04/01/2008 |
| 7350132 | Nanoscale interconnection interface One embodiment of the present invention provides a demultiplexer implemented as a nanowire crossbar or a hybrid nanowire/microscale-signal-line crossbar with resistor-like nanowire junctions. The demultiplexer of one embodiment provides demultiplexing of signals inp... | 03/25/2008 |
| 7350137 | Method and circuit for error correction in CAM cells A method and circuit is provided for detecting and correcting errors in an array of content addressable memory (CAM) cells. The array includes wordlines, searchlines, bitlines, and matchlines for reading from, writing to, and searching CAM cells in the array. The me... | 03/25/2008 |
| 7350126 | Method for constructing erasure correcting codes whose implementation requires only exclusive ORs Error correcting codes of any distance (including codes of distance greater than four) use only exclusive OR (XOR) operations. Any code over a finite field of characteristic two are converted into a code whose encoding and correcting algorithms involve only XORs of ... | 03/25/2008 |
| 7343432 | Message based global distributed locks with automatic expiration for indicating that said locks is expired Described is a distributed lock processing technique that may be used to coordinate access to globally accessed resource between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fa... | 03/11/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7340665 | Shared redundancy in error correcting code A method and apparatus are provided for storing data. The method and apparatus generate a plurality of ECC codewords, which define a cooperative block. Each ECC codeword includes a plurality of information symbols and first and second sets of corresponding redundanc... | 03/04/2008 |
| 7337352 | Cache entry error-connecting code (ECC) based at least on cache entry data and memory address Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry in... | 02/26/2008 |
| 7333232 | Image processing apparatus having a function to receive control programs transferred from external device An image processing apparatus avoids abnormal control on loads including an optional device and enables only program transfer when transfer of a control program from an external device is not normally proceeding. Through a communication interface, the control progra... | 02/19/2008 |
| 7331043 | Detecting and mitigating soft errors using duplicative instructions Software techniques are employed to mitigate soft errors. In particular, a compiler (or other executable code generator) may emit otherwise duplicative instructions targeting otherwise duplicative storage locations to facilitate run-time detection and, in some cases... | 02/12/2008 |
| 7328305 | Dynamic parity distribution technique A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file system with a RAID system. In response to a request to store (write) dat... | 02/05/2008 |
| 7324995 | Method for retrieving and modifying data elements on a shared medium A method for retrieving and modifying data elements on a shared medium following request from multiple client computers, such that data retrieval transactions on a data element, originating from one or more clients, are not compromised by data update transactions on... | 01/29/2008 |
| 7325019 | Managing data replication policies An application implemented on a server in a network of storage servers can be provided to manage the data replication relationships implemented between the storage servers of the network. In one embodiment, this server can be designated the manager server, and can p... | 01/29/2008 |
| 7321997 | Memory channel self test A buffer logic within a memory module having the capability to carry out a test of another memory module to which it is coupled via a point-to-point bus through autonomously storing and transmitting a test pattern across that point-to-point bus to the other memory m... | 01/22/2008 |
| 7304875 | Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in sel... | 12/04/2007 |
