Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 8190981 | Apparatus and method for transmitting and receiving data in a communication system using low density parity check codes An apparatus for transmitting data in a communication system using a Low Density Parity Check (LDPC) matrix is provided. The apparatus includes an interleaver for interleaving a descending bit-ordered codeword having a predetermined size and in accordance with a pre... | 05/29/2012 |
| 8181099 | Transmission device Disclosed is a transmission device in a communication system in which a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deleting the dummy bits from the results of the systematic encoding is transmitted a... | 05/15/2012 |
| 8176403 | Distributed block coding (DBC) Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where t... | 05/08/2012 |
| 8161363 | Apparatus and method to encode/decode block low density parity check codes in a communication system An apparatus and method to encode a block Low Density Parity Check (LDPC) code in a signal transmission apparatus is disclosed. The method includes generating a first block LDPC codeword by encoding an information vector using a first parity check matrix when a code... | 04/17/2012 |
| 8151176 | CPU instruction RAM parity error procedure A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor,... | 04/03/2012 |
| 8145986 | Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employe... | 03/27/2012 |
| 8132086 | Semiconductor memory device for byte-based masking operation and method of generating parity data A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating ... | 03/06/2012 |
| 8132087 | Forward error correction mapping and de-mapping techniques Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame. ... | 03/06/2012 |
| 8122334 | Parity error detecting circuit and method A parity error detecting circuit includes a first operation unit, a second operation unit, and a shift register. The first operation unit receives a serial data signal and a first signal, performs a logic operation on the two received signals, and outputs the result... | 02/21/2012 |
| 8117523 | Rate-compatible protograph LDPC code families with linear minimum distance Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node wit... | 02/14/2012 |
| 8108762 | Operating method and circuit for low density parity check (LDPC) decoder An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated chec... | 01/31/2012 |
| 8095859 | Encoder for low-density parity check codes Encoding of a low-density parity check code uses a block-circulant encoding matrix built from circulant matrices. Encoding can include partitioning data into a plurality of data segments. The data segments are each circularly rotated. A plurality of XOR summations a... | 01/10/2012 |
| 8095860 | Method for implementing stochastic equality nodes The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding ... | 01/10/2012 |
| 8086945 | Tensor product codes containing an iterative code Systems and methods are provided for encoding a stream of datawords based on a tensor product code to provide a stream of codewords, and detecting and decoding a stream of received data based on a tensor product code to provide a decoded stream of data. In one aspec... | 12/27/2011 |
| 8078949 | Semiconductor memory device A semiconductor memory device includes: a parity generating circuit for generating parity data corresponding to input data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for ... | 12/13/2011 |
| 8055987 | Apparatus and method for transmitting and receiving signal in a communication system An apparatus and method for transmitting and receiving a signal in a communication system are provided. The signal transmission apparatus generates a parity check matrix for an LDPC code in accordance with a code rate to be used and generates a codeword vector by en... | 11/08/2011 |
| 8028224 | Method and system for providing short block length low density parity check (LDPC) codes An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an L... | 09/27/2011 |
| 8028223 | Transmission device, encoding device and decoding device Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are... | 09/27/2011 |
| 7930622 | Method of encoding and decoding adaptive to variable code rate using LDPC code A variable code rate adaptive encoding/decoding method using LDDC code is disclosed, in which an input source data is encoded using the LDPC (low density parity check) code defined by a first parity check matrix configured with a plurality of submatrices. The presen... | 04/19/2011 |
| 7925965 | Method for transmitting/receiving signals in a communications system and an apparatus therefor A method for transmitting a signal in a signal transmission apparatus of a communications system including receiving an information vector, and encoding the information vector according to a zigzag B-LDPC encoding scheme to generate a zigzag B-LDPC codeword, thereby... | 04/12/2011 |
| 7900126 | Systems and methods for reduced complexity LDPC decoding Systems and methods for generating check node updates in the decoding of low-density parity-check (LDPC) codes use new approximations in order to reduce the complexity of implementing a LDPC decoder, while maintaining accuracy. The new approximations approximate the... | 03/01/2011 |
| 7895509 | Error checking parity and syndrome of a block of data with relocated parity bits Method and apparatus for error checking information is described. Configuration data includes data bits and parity bits. Notably, parity bits may be relocated for determining a syndrome value. Syndrome bits are determined by computing a partial syndrome value for ea... | 02/22/2011 |
| 7849390 | Data communication module providing fault tolerance and increased stability A module for transmitting sets of data bits to another module via a communication bus using dual-rail encoding is provided that has a reduced switching activity. The module comprises bus invert coding means adapted to compare a set of data bits with a preceding set ... | 12/07/2010 |
| 7805665 | Parity engine for use in storage virtualization controller and method of generating data by parity engine A parity engine for use in a storage virtualization controller includes a control unit being a control kernel of the parity engine; a control unit buffer serving as a data buffer of the control unit and storing map tables required for operations; at least one XOR en... | 09/28/2010 |
| 7802172 | Variable-rate low-density parity check codes with constant blocklength Low density parity check (LDPC) codes (LDPCCs) have an identical code blocklength and different code rates. At least one of the rows of a higher-rate LDPC matrix is obtained by combining a plurality of rows of a lower-rate LDPC matrix with the identical code blockle... | 09/21/2010 |
| 7793203 | Fieldbus process communications using error correction A method of communicating over an H1 Fieldbus network is provided. The communication over the H1 Fieldbus network employs an advanced form of error correction. In one embodiment, the advanced form of error correction utilizes low-density parity check codes; while in... | 09/07/2010 |
| 7779341 | NAND flash memory device performing error detecting and data reloading operation during copy back program operation A NAND flash memory device performing an error detecting and data reloading operation during a copy back program operation is provided. The device includes a cell array having a plurality of planes and a parity cell array having a plurality of parity planes. Each of... | 08/17/2010 |
| 7774690 | Apparatus and method for detecting data error A semiconductor circuit includes a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU; a register configured to hold the data with the parity bit; and a parity check circuit configured to execute a parity check of said data with s... | 08/10/2010 |
| 7743315 | System and method for low-density parity check (LDPC) code design Disclosed is a density evolution algorithm based on a refined definition of node and edge densities for different parts of the code. In particular, density functions ƒV(1)(i) and ƒV(2)(i) of the output edges of the varia... | 06/22/2010 |
| 7734993 | Method and apparatus for encoding and precoding digital data within modulation code constraints Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation e... | 06/08/2010 |
| 7698625 | System for improving parity generation and rebuild performance A dual parity hardware architecture that enables data to be read from each sector only once and performs both the P parity and Q parity from the single data source. The Q parity calculator provides parallel processing capabilities so that multiple parity operations ... | 04/13/2010 |
| 7681111 | Disk array device, parity data generating circuit for RAID and Galois field multiplying circuit In this parity data generating circuit, a Galois field multiplying calculation is realized by performing data conversion by index table information generated from a Galois field multiplying table so that data for RAID6 are generated. A table check circuit inspects n... | 03/16/2010 |
| 7673226 | Method and system for providing short block length low density parity check (LDPC) codes An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an L... | 03/02/2010 |
| 7636880 | Error correction scheme for memory An embedded DRAM ECC architecture for purging data errors. The embedded DRAM ECC architecture is based upon a two-dimensional linear parity scheme, and includes a plurality of memory blocks and a parity block. Each memory block includes additional columns for storin... | 12/22/2009 |
| 7617442 | Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. ... | 11/10/2009 |
| 7600180 | Iterative metric updating when decoding LDPC (low density parity check) coded signals and LDPC coded modulation signals Iterative metric updating when decoding LDPC (Low Density Parity Check) coded signals and LDPC coded modulation signals. A novel approach is presented for updating the bit metrics employed when performing iterative decoding of LDPC coded signals. This bit metric upd... | 10/06/2009 |
| 7519898 | Iterative decoding of linear block codes by adapting the parity check matrix A method of decoding linear block code uses an iterative message passing algorithm with a binary image of a parity check matrix of the linear block code, wherein the parity check matrix is adapted from one iteration to another based on the reliabilities of bits in t... | 04/14/2009 |
| 7484168 | Parity check outer code and runlength constrained outer code usable with parity bits The invention provides a channel coding method for encoding systematic data for transmission in a communication channel. The systematic data has a runlength constraint. In the method, data words are permuted. Error codes are generated based upon the permuted data wo... | 01/27/2009 |
| 7484167 | Error detection using codes targeted to prescribed error types Techniques are described for detecting error events in codewords detected from data signals transmitted via a communication system. The error events are detected with an error detection code that corresponds to one or more dominant error events for the communication... | 01/27/2009 |
| 7451386 | LDPC (Low Density Parity Check) coded modulation hybrid decoding LDPC (Low Density Parity Check) coded modulation hybrid decoding. A novel approach is presented wherein a combination of bit decoding and symbol level decoding (e.g., hybrid decoding) is performed for LDPC coded signals. Check node updating and symbol node updating ... | 11/11/2008 |
