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3M employee and church chorister Art Fry needed something to temporarily mark pages in his hymnal. He was in luck because his colleague, Spencer Silver, accidentally developed a glue that was too weak for other purposes. After initially discouraging consumer response, Post-it Notes became a hit in 1979.
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| Number | Title | Issue Date |
| 8095858 | File error identification, reporting, and replacement of media files The present invention discloses a solution for automatically replacing a media files upon a device able to identify problems with locally stored media files. Initially, an automated process or user of a media playing device can initially identify a media file, which... | 01/10/2012 |
| 8078948 | Two-phase data-transfer protocol A data communication arrangement permits efficient data transfer between a controller module and multiple target modules using a two-phase protocol. The controller module and the target modules can each reside in separate clock domains. Consistent with one example e... | 12/13/2011 |
| 8065597 | Self test of plesiochronous interconnect A method and apparatus for performing a self-test of a plesiochronous link. A pseudorandom serial bit pattern is generated by the transmitter from a linear feedback shift register (LFSR) based on a primitive polynomial of a specific order and transmitted across a pl... | 11/22/2011 |
| 7996750 | Lip synchronization system and method A system and method for correcting so-called “lip sync” errors is provided, using a synchronization test signal comprising a video signal including a colorbar signal that is periodically interrupted by a series of consecutive defined black frames and an audio si... | 08/09/2011 |
| 7908546 | Methods and apparatus for detection of performance conditions in processing system Techniques are disclosed for detection of performance conditions in processing systems. For example, a method of detecting a performance condition in at least one particular processing device of a processing system having a plurality of processing devices includes t... | 03/15/2011 |
| 7844887 | Bit error probability estimation method and receiver emplying the same A bit error probability (BEP) estimation method includes de-shaping a coded block to obtain a channel hard output block comprising a header hard output and at least one data hard output, de-puncturing and decoding the header hard output to obtain a decoded header pa... | 11/30/2010 |
| 7836386 | Phase shift adjusting method and circuit Method and system of adjusting a first phase shift between a first data signal and a clock signal at a sending device. First and second test signals representing first and second test data, respectively, are transmitted to a receiving device. The test signals have r... | 11/16/2010 |
| 7712014 | Synchronizing clock and aligning signals for testing electronic devices A testing circuit includes a signal generator operative to provide a control signal in response to a reference clock signal. The control signal may include both alignment and timing information operative to synchronize the timing and output of the signal generator w... | 05/04/2010 |
| 7702992 | Semiconductor integrated circuit with flip-flops having increased reliability A semiconductor integrated circuit includes a plurality of flip-flop sets, and a logic circuit configured to consolidate error-detection signals output from the flip-flop sets into one output signal, wherein each of the flip-flop sets includes one or more flip-flops... | 04/20/2010 |
| 7665011 | Method and circuit for reducing SATA transmission data errors by adjusting the period of sending align primitives A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period... | 02/16/2010 |
| 7506240 | Method and apparatus for image processing The present application relates to a method of at least substantially synchronizing data output from at least first and second graphics cards (1, 2). A synchronization difference between the first graphics card (1) and the second graphics card (2 | 03/17/2009 |
| 7484166 | Semiconductor integrated circuit verification method and test pattern preparation method In the inventive semiconductor integrated circuit verification method, based upon expected values of a signal from an integrated circuit, which are obtained by RTL verification or the like, and upon signal delay information obtained by static timing analysis (STA), ... | 01/27/2009 |
| 7480853 | Deleting objects from a store of a device Systems, methods, and computer program products for deleting objects from device stores without deleting corresponding objects from one or more synchronization partners. A device has a device sync module for each synchronization partner and each device sync module m... | 01/20/2009 |
| 7472336 | Data detector and multi-channel data detector A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a ... | 12/30/2008 |
| 7444275 | Multi-variable polynomial modeling techniques for use in integrated circuit design Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage s... | 10/28/2008 |
| 7437656 | Error correction of balanced codeword sequence A method for recoding an input sequence of words, including assigning a respective bit-grade to at least one of the bits in a first word in the input sequence, deriving candidate words from the first word in response to the respective bit-grade, and inserting one of... | 10/14/2008 |
| 7428283 | Data recovery algorithm using data position detection and serial data receiver adopting the same The present invention relates generally to a data recovery algorithm and a serial link data receiver adopting the same. The data recovery algorithm includes receiving a serial data stream and a reference clock signal from a transmitting end, generating a plurality o... | 09/23/2008 |
| 7424307 | Loss of page synchronization Systems and methods for maintaining data stream synchronization are provided. A system comprises one or more radio head interface modules and a call processing software module each adapted to communicate with each other. The call processing software module performs ... | 09/09/2008 |
| 7418650 | Method for temporal synchronization of clocks In order to carry out in a communication system (1) a temporal synchronization of clocks in a particularly rapid and efficient manner, a method is proposed which has the following steps: acquiring state values which are dependent on a time base (10); f... | 08/26/2008 |
| 7409631 | Error-detection flip-flop An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a ... | 08/05/2008 |
| 7406652 | Method and circuit for reducing SATA transmission data errors by adjusting the period of sending ALIGN primitives A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period... | 07/29/2008 |
| 7404115 | Self-synchronising bit error analyser and circuit A self-synchronising data bus analyser comprising a generator LFSR, a receiver LFSR and a comparator wherein the generator LFSR generates a first data set which is transmitted through a data bus to the comparator; and wherein the comparator... | 07/22/2008 |
| 7372928 | Method and system of cycle slip framing in a deserializer A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit s... | 05/13/2008 |
| 7369811 | System and method for sensitivity optimization of RF receiver using adaptive nulling The present invention provides sensitivity enhancement for a single antenna RFID interrogating device by separately coupling a nulling signal formed using a portion of a transmit signal into a receiver. The phase and amplitude of nulling signal can be adjusted so th... | 05/06/2008 |
| 7370247 | Dynamic offset compensation based on false transitions A method and apparatus provide a receiver with an architecture to regulate a bit error rate of the receiver using an offset based on detecting false transitions in received data. In an embodiment, such false transitions in data may be determined in a bang-bang detec... | 05/06/2008 |
| 7369634 | Training pattern for a biased clock recovery tracking loop Some embodiments of the invention provide a biased tracking loop that may include encoded information. Embodiments may comprise a training pattern, utilized in a non-interfering way that allows for clock recovery, embedded information transmission and/or header alig... | 05/06/2008 |
| 7370239 | Input/output device with configuration, fault isolation and redundant fault assist functionality A process control system includes a plurality of input/output (I/O) devices and a controller in communication using a bus. Each I/O device has an interface for communicatively linking the I/O device with the bus, and includes a device processor which, upon detection... | 05/06/2008 |
| 7370256 | Integrated circuit testing module including data compression Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit a... | 05/06/2008 |
| 7366477 | Redundancy version implementation for an uplink enhanced dedicated channel This invention describes a method for a redundancy version implementation of an uplink (UL) enhanced dedicated channel (E-DCH) in mobile communication systems by calculating a redundancy version number (RVN) as a function of a connection frame number (CFN), a maximu... | 04/29/2008 |
| 7363431 | Message-based distributed synchronization in a storage system Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint wi... | 04/22/2008 |
| 7362837 | Method and apparatus for clock deskew A clock signal is deskewed relative to a data signal by sweeping a sampling point in time and sweeping an amplitude offset. Bit error measurements are made at each sampling point in time and compared. Bit error measurements may be made by comparing received data to ... | 04/22/2008 |
| 7359823 | RFID device variable test systems and methods Systems and methods are disclosed herein to provide variable test techniques for RFID devices. For example, in accordance with an embodiment of the present invention, a radio frequency identification (RFID) test system includes an RFID reader adapted to provide an R... | 04/15/2008 |
| 7359367 | Device for preventing erroneous synchronization in wireless communication apparatus An erroneous synchronization preventing device includes a pattern detector detecting a sync pattern from received data with a broader sync window to output a sync detection notice and a sync timing. On receipt of the notice, a packet header detector checks an error ... | 04/15/2008 |
| 7356756 | Serial communications data path with optional features Integrated circuits compliant with a serial communications protocol with optional and adjustable features are provided. Tools for designing such circuits are also provided. The protocol supports different data transmission modes such as streaming data and packetized... | 04/08/2008 |
| 7353350 | Data store management system and method for wireless devices In accordance with the teaching described herein, systems and methods are provided for managing memory space in a mobile device. A plurality of data storage locations may be included. A plurality of software applications may be included, with each software applicati... | 04/01/2008 |
| 7342969 | Signaling with multiple clocks At least two sequences of predetermined reference times are established on respective ones of at least two communication lines. At least some of the reference times of at least one of the sequences occur out-of-phase with at least some of the reference times of anot... | 03/11/2008 |
| 7340657 | On-chip high-speed serial data analyzers, systems, and associated methods In an embodiment, a method includes forming a plurality of time/voltage points from a number of voltage values and from a number of time values, generating serialized data having a predetermined number of bits, comparing the serialized data to a set predetermined vo... | 03/04/2008 |
| 7340656 | Method and apparatus for probing a computer bus The subject invention facilitates the efficient operation of the disassembly of the microprocessor bus by providing an apparatus and method for detecting and correcting a strobe phase inversion and predrive filtering in a 2× source synchronous data transfer bus. Ap... | 03/04/2008 |
| 7339853 | Time stamping events for fractions of a clock cycle Generally, the embodiments are directed to circuits and methods for time stamping an event at a fraction of a clock cycle. A time stamping circuit comprises two or more detection circuits. The detection circuits receive an event-in signal and generate event signals ... | 03/04/2008 |
| 7337356 | Systematic and random error detection and recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture e... | 02/26/2008 |
