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| Number | Title | Issue Date |
| 8145984 | Reading memory cells using multiple thresholds A method for operating a memory (28) includes storing data, which is encoded with an Error Correction Code (ECC), in analog memory cells (32) of the memory by writing respective analog input values selected from a set of nominal values to the analog me... | 03/27/2012 |
| 8086944 | Hard disk drive with data error recovery using multiple reads and derived reliability information A hard disk drive with a disk that has a plurality of data bits. The drive includes a circuit that reads each data bit n times and selects a value for the bit based on a reliability factor. The circuit may select a bit based at least in part on the most frequent occ... | 12/27/2011 |
| 7870471 | Methods and apparatus for employing redundant arrays to configure non-volatile memory Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redu... | 01/11/2011 |
| 7870472 | Methods and apparatus for employing redundant arrays to configure non-volatile memory Systems, methods and apparatus are disclosed for employing redundant arrays to configure non-volatile memory. The present invention may include a substrate including a plurality of memory arrays, wherein the memory arrays include a data array and at least three redu... | 01/11/2011 |
| 7620883 | Techniques for mitigating, detecting, and correcting single event upset effects SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic out... | 11/17/2009 |
| 7539931 | Storage element for mitigating soft errors in logic In a preferred embodiment, the invention provides a method for reducing soft errors in logic. After obtaining two delayed clock signals, the delayed clock signals, the clock signal, and an output from a logic circuit are applied to a triple redundant memory element.... | 05/26/2009 |
| 7536631 | Advanced communication apparatus and method for verified communication A communication circuit for verified communication comprising a transmitter having input terminals to receive a data word, an encoder configured to encode the data word to create an encoded word different from the data word, and output terminals configured to transm... | 05/19/2009 |
| 7512871 | Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays SEU mitigation, detection, and correction techniques are disclosed. Mitigation techniques include: triple redundancy of a logic path extended the length of the FPGA; triple logic module and feedback redundancy provides redundant voter circuits at redundant logic out... | 03/31/2009 |
| 7509567 | System and method for resolving data inconsistencies with a data majority A system and method for an election and data majority mechanism that solves problems such as bit flipping, mistracking, miscaching, and I/O status errors during real-time operations. Multiple copies of data are stored on various storage media of a data processing sy... | 03/24/2009 |
| 7451384 | Error recovery in asynchronous combinational logic circuits A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necess... | 11/11/2008 |
| 7444565 | Re-programmable COMSEC module A method of mitigating logic upsets includes providing an input to each of a plurality of programmable logic components, processing the input in each programmable logic component, determining an output from each programmable logic component, providing the output fro... | 10/28/2008 |
| 7428473 | Health monitoring in a system of circumvention and recovery A system comprises at least one non-hardened processor configured to run a plurality of mission related processes; at least one threat detector configured to detect one or more conditions which indicate the onset of a threat to the operation of the at least one non-... | 09/23/2008 |
| 7424642 | Method for synchronization of a controller A system and method for reintegration of a redundant controller after occurrence of a fault is provided, comprising synchronizing outputs of a primary controller with outputs of secondary controllers. The controller is placed in a different mode of operation in whic... | 09/09/2008 |
| 7418641 | Self-resetting, self-correcting latches A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit u... | 08/26/2008 |
| 7372304 | System and method for glitch detection in a secure microcontroller An apparatus includes a plurality of macrocells formed from logic capable of performing one or more functions. The apparatus also includes a clock tree capable of receiving a clock signal and providing at least one copy of the clock signal to each macrocell. The clo... | 05/13/2008 |
| 7366968 | Data processing apparatus, and its processing method, program product and mobile telephone apparatus A data processing apparatus capable of preventing contention of memory access between the HARQ synthesis and rate dematching in the HARQ processing using two or more single-port memories is provided. A buffer includes two physical memories. One of the physical memor... | 04/29/2008 |
| 7366727 | Management of inbound conflicts when merging data of distributed systems A method, a computer program, a computer program product, and a system for checking data consistency of data objects of distributed systems within a computer network are disclosed. System objects may be automatically merged with inbound objects by sending a first da... | 04/29/2008 |
| 7366983 | Spell checker with arbitrary length string-to-string transformations to improve noisy channel spelling correction A spell checker based on the noisy channel model has a source model and an error model. The source model determines how likely a word w in a dictionary is to have been generated. The error model determines how likely the word w was to have been incorrectly entered a... | 04/29/2008 |
| 7363546 | Latent fault detector A latent error detector may be configured to reveal latent errors within a plurality of components within a computer system. The latent error detector may be configured to access configuration data specifying one or more types of components and one or more modules f... | 04/22/2008 |
| 7363533 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit ser... | 04/22/2008 |
| 7360253 | System and method to lock TPM always ‘on’ using a monitor A computer may be secured from attack by including a trusted environment used to verify a known monitor. The monitor may be used to determine a state of the computer for compliance to a set of conditions. The conditions may relate to terms of use, such as credits av... | 04/15/2008 |
| 7353433 | Poisoned error signaling for proactive OS recovery Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered. ... | 04/01/2008 |
| 7350136 | Voting system for improving the performance of single-user decoders within an iterative multi-user detection system A system is presented that provides real-time performance for iterative multi-user detectors, such as Turbo MUDs, which are used to separate simultaneous transmissions on the same frequency, by permitting the MUD to use a less computationally intense, fast-processin... | 03/25/2008 |
| 7337044 | Dual/triplex flight control architecture A flight control computer for controlling an actuator responsive to a flight control command is described. The system includes a first, second, and third pair of processors. Three different processor types make up the three pairs of processors and the pairs of proce... | 02/26/2008 |
| 7333099 | Electronic circuit, display device, and electronic apparatus A current data compression circuit of which output current value is accurate even when transistors with large variations in electrical characteristics are used. The current data compression circuit is an electronic circuit comprising a drive element including a plur... | 02/19/2008 |
| 7334014 | Consistent time service for fault-tolerant distributed systems A consistent time service that provides a method of maintaining deterministic clock-related operations for a group of replicas in a fault-tolerant distributed system. A consistent clock synchronization algorithm is utilized that yields a single consistent group cloc... | 02/19/2008 |
| 7328369 | Inherently fail safe processing or control apparatus A processing/control apparatus has a first processing unit with a first data processor/controller; an input port for input data received from a remote unit; an output port for output data to be transmitted to a remote unit. The first unit comprising device for gener... | 02/05/2008 |
| 7318175 | Memory modeling circuit with fault toleration A memory modeling circuit with fault toleration includes a compare circuit, a control circuit and a test circuit. The compare circuit receives the data stored in the same address of memories and compares data with each other to produce the correct reading data. The ... | 01/08/2008 |
| 7318169 | Fault tolerant computer A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long in... | 01/08/2008 |
| 7313552 | Boolean network rule engine A Boolean Network rule engine for evaluation of rules is described that comprises: a rules interface for receiving a set of rules, each rule having at least one condition; a network builder for building a Boolean Network representation of the set of rules including ... | 12/25/2007 |
| 7313717 | Error management A computer system includes a plurality of field replaceable units. A system controller monitors system errors. A diagnostic engine is responsive to the system controller detecting an error to identify a faulty field replaceable unit. A reconfiguration engine can the... | 12/25/2007 |
| 7313748 | FEC decoder and method A method is described for FEC decoding a signal which has become affected by transmission errors, the original signal being transmitted together with parity data. The method comprises: receiving (5) the original signal (DATA) and parity data (ECC DATA) with e... | 12/25/2007 |
| 7313037 | RFID system including a memory for correcting a fail cell and method for correcting a fail cell using the same A radio frequency identification (RFID) system and a method for correcting a failed cell using the same are provided. The RFID system effectively corrects randomly distributed cell data by using a failed cell correcting circuit in a memory. In the RFID system, a pre... | 12/25/2007 |
| 7308605 | Latent error detection In an implementation of latent error detection, memory regions that each correspond to a different processor element of a redundant processor system are scanned for latent processing errors maintained as erroneous data. The data maintained in the memory regions is c... | 12/11/2007 |
| 7305213 | Receiver and wireless LAN apparatus in which a received signal is correlated to a reference symbol A receiver comprising: an antenna which receives a radio signal including N possible symbols {c1(n), c2(n), . . . cM−1(n), cM(n)}, an N correlation units which are provided cor... | 12/04/2007 |
| 7296183 | Selectable data field consistency checking A system consistency management module that performs consistency checking on behalf of an instance. The module identifies data fields of state information corresponding to the instance that are to be subject to consistency checking. The instance may identify this da... | 11/13/2007 |
| 7280468 | Apparatus for constant amplitude coded bi-orthogonal demodulation A constant amplitude coded bi-orthogonal demodulator demodulates the received constant amplitude bi-orthogonal modulated data, cancels the parity bits to generate the serial data, detects the occurrence of an error by dividing the demodulated data into a plurality o... | 10/09/2007 |
| 7269780 | Power management for circuits with inactive state data save and restore scan chain An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the s... | 09/11/2007 |
| 7263630 | Fault tolerant computer controlled system An error tolerant computer controlled system comprises several computers working redundantly and controlling actuators based on signals from sensors and input devices. Each data item emitted by each computer is simultaneously sent through differing communication pat... | 08/28/2007 |
| 7259602 | Method and apparatus for implementing fault tolerant phase locked loop (PLL) A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes a divide by N circuit defined by a plurality of sub-divide by N functions, each providing a feedback frequency signal applied to a voter circuit. ... | 08/21/2007 |
