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| Number | Title | Issue Date |
| 7770094 | Apparatus and method for soft decision viterbi decoding When a convolution code is decoded, electric power consumption is suppressed keeping error correction capability. In a Viterbi decoder which decodes received signal, a convolution code, having plural series with a soft decision Viterbi decoding method, an estimation... | 08/03/2010 |
| 7765458 | Error pattern generation for trellis-based detection and/or decoding The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that w... | 07/27/2010 |
| 7765459 | Viterbi decoder and viterbi decoding method The present invention relates to a Viterbi decoder and a Viterbi decoding method in a register exchange method. The Viterbi decoder receives an encoded bit sequence of a convolutional encoding method from a channel, generates an expanded encoded bit sequence by cycl... | 07/27/2010 |
| 7752531 | Defect sensing Viterbi based detector A detector includes a Viterbi based detector and an erasure detector that detects as erasures one or more bits associated with a decoding window in which survivor paths do not merge within the decoding window. ... | 07/06/2010 |
| 7743313 | System for impulse noise and radio frequency interference detection A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first e... | 06/22/2010 |
| 7734992 | Path memory circuit A path memory circuit for use in a Viterbi decoding process performed based on state transitions through a number n (n is a positive integer) of states. The path memory circuit includes a memory area A formed by the storage circuits of the first to ith (i... | 06/08/2010 |
| 7725809 | Signal quality evaluation device, information read/write device, signal quality evaluation method, write conditions determining method, signal quality evaluation computer program, computer-readable storage medium containing signal quality evaluation computer program A Viterbi decoding circuit performs Viterbi decoding on the basis of a reproduced signal obtained by reading an optical disc. A decoded bit sequence is fed to a first specific pattern detection circuit and a first reverse pattern detection circuit. A path metric dif... | 05/25/2010 |
| 7716565 | Method and system for decoding video, voice, and speech data using redundancy A method and system for decoding video, voice, and/or speech data using redundancy and physical constraints are presented. Video, voice, and/or speech bit sequences may be decoded in a multilayer process based on a decoding algorithm and at least one physical constr... | 05/11/2010 |
| 7673224 | Low power viterbi decoder using a novel register-exchange architecture An apparatus and method of reducing power dissipation in a register exchange implementation of a Viterbi decoder used in a digital receiver or mass-storage system without degrading the bit error rate of the decoder, by selectively inhibiting data samples in the Vite... | 03/02/2010 |
| 7669110 | Trace-ahead method and apparatus for determining survivor paths in a Viterbi detector Methods and apparatus are provided for determining survivor paths in a Viterbi detector, using a trace-ahead algorithm. A trellis memory is maintained having a depth L that stores L trellis stages, each of the L stages having a plurality, N, of trellis states; and a... | 02/23/2010 |
| 7650561 | Method of switching from parallel to serial MAP detector A MAP detector system operates in a parallel mode for on-the-fly operations and in a serial mode for error recovery operations. In the parallel mode, a plurality of Viterbi operators process a block of input sampled data in parallel. In the serial mode a selected fo... | 01/19/2010 |
| 7644346 | Format detection A method of assessing an encoded signal to determine whether a candidate format was used to arrange the signal into blocks before the encoding was done, the method comprising: using the Viterbi algorithm to determine trellis metrics for a point in said signal that w... | 01/05/2010 |
| 7636879 | Error correction decoder An error correction decoder possessing a decoding method with high error correction performance and capable of operating at a low operating frequency and on a reduced circuit scale. A decoding method based on the SOVA method for improving error correction performanc... | 12/22/2009 |
| 7634714 | Decoding system for eight-to-fourteen modulation or eight-to-sixteen modulation A decoding system for eight-to-fourteen modulation or eight-to-sixteen modulation (EFM/ESM), which has an analog to digital converter (ADC), an adaptive equalizer and a Viterbi decoder. The ADC receives an analog signal with an EFM or ESM feature, and converts the a... | 12/15/2009 |
| 7617440 | Viterbi traceback initial state index initialization for partial cascade processing This invention provides the correct Viterbi decode traceback starting index is obtained for all constraint lengths and frame sizes. Reverse transpose operations that depend on the last active add-compare-select unit a cascade block of the state metric update process... | 11/10/2009 |
| 7613989 | Decoder for executing a Viterbi algorithm A Viterbi decoder includes a computing device, a memory and a bus. The computing device receives sets of data values and calculates distances for the received sets of data values, accumulates and compares the calculated distances according to a Viterbi algorithm, de... | 11/03/2009 |
| 7607073 | Methods, algorithms, software, circuits, receivers and systems for iteratively decoding a tailbiting convolutional code Methods, software, circuits and systems involving a low complexity, tailbiting decoder. The method relates to appending and/or prepending data subblocks to a serial data block, decoding and estimating starting and ending states for the serial data block, and when th... | 10/20/2009 |
| 7603613 | Viterbi decoder architecture for use in software-defined radio systems A reconfigurable Viterbi decoder comprising a reconfigurable data path and a programmable finite state machine that controls the reconfigurable data path. The reconfigurable data path comprises a plurality of reconfigurable functional blocks including: i) a reconfig... | 10/13/2009 |
| 7590927 | Soft output viterbi detector with error event output Outputting information for recovering a sequence of data is disclosed. Outputting includes making a decision that selects a first sequence of states corresponding to a surviving path, determining a second sequence of states corresponding to a non-surviving path asso... | 09/15/2009 |
| 7590928 | Apparatus and method for Viterbi decoding A Viterbi decoding apparatus and a method thereof are disclosed. According to each partial surviving path formed by the decision information of every k continuous symbols of a symbol sequence, the apparatus can write its start trellis state and corresponding partial... | 09/15/2009 |
| 7587660 | Multiple-access code generation Multiple-access codes are generated using an asymptotically optimal decoding algorithm, such as the Viterbi algorithm. A trellis may be constructed using a number of desired users, at least one code length, and a number of code-chip parameters. A fitness function is... | 09/08/2009 |
| 7584408 | Viterbi path generation for a Dynamic Bayesian Network Methods, systems, and apparatus are provided to generate a Viterbi path for a DBN. The DBN is converted to a chain of junction trees, where each tree represents a decision-making process. The trees are forwardly iterated and the Viterbi path is generated during the ... | 09/01/2009 |
| 7581160 | ACS circuit and Viterbi decoder with the circuit An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to genera... | 08/25/2009 |
| 7571376 | Viterbi decoder for executing trace-back work in parallel and decoding method A Viterbi decoder for executing a trace-back work in parallel and a decoding method. The Viterbi decoder includes a branch metric calculator which calculates a branch metric from a branch code passing each state on a trellis diagram and a predetermined input code, a... | 08/04/2009 |
| 7565600 | Method for determining output signals of a Viterbi decoder The present invention provides a method for determining output signals of a Viterbi decoder. Firstly, in step (a), a plurality of digital signals are received through a path memory module of the Viterbi decoder with decoding an input signal; in step (b) the received... | 07/21/2009 |
| 7533329 | Method for simplifying a viterbi decoder and a simplified viterbi decoder using the same A method for simplifying a Viterbi decoder includes receiving a partial response, and determining an amount of redundant selector modules according to a tap number of the partial response; analyzing an output signal of the redundant selector modules for determining ... | 05/12/2009 |
| 7512869 | Convolutional decoding In one aspect the invention is a method for sequence estimating. The method includes receiving convolutional codes. The method further includes using a lazy Viterbi decoder to decode the convolutional codes. The convolutional codes may be stream convolutional codes.... | 03/31/2009 |
| 7512870 | Method and system for improving the performance of a trellis-based decoder Method and system are provided for improving the performance of a trellis-based decoder. States with reduced uncertainty (SRUs) are defined for one or more predetermined fields in an encoded message. Metrics are set for the SRUs such that candidate paths through a t... | 03/31/2009 |
| 7506239 | Scalable traceback technique for channel decoder Apparatus, system, and method for scalable traceback techniques for channel decoding are described. ... | 03/17/2009 |
| 7490284 | Meta-Viterbi algorithm for use in communication systems Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel characterized by intersymbol interference. Each of the one or more codewords incorporates one ... | 02/10/2009 |
| 7478315 | Parallel spectral equalization channels with low density parity check codes The present invention combines low density parity checking with parallel equalization channels to enhance data retrieval from tape. Viterbi analysis is done as a precursor to the use of at least one low density parity decoder. A signal decoder may include a pluralit... | 01/13/2009 |
| 7447983 | Systems and methods for decoding forward error correcting codes Systems and methods for improving the performance of decoders of forward error correcting codes use the information contained in late packet arrivals to update (or recompute) the state of the decoder. These systems and methods are generally applicable to decoders th... | 11/04/2008 |
| 7443936 | Sequence detector using Viterbi algorithm with reduced complexity sequence detection via state reduction using symbol families A sequence detector (1600-w) operating generally according to the Viterbi algorithm uses state reduction via division into symbol families to reduce the complexity of sequence detection. The sequence detector contains a branch metric generator (1402-w)... | 10/28/2008 |
| 7441177 | Information reproduction apparatus and method using maximum likelihood decoding An information reproduction apparatus using maximum likelihood decoding for calculating likelihood of a value of a reproducing signal to a plurality of reference values, the reproducing signal obtained from a recording medium, to decode the reproducing signal on the... | 10/21/2008 |
| 7441174 | Embedded state metric storage for MAP decoder of turbo codes A method, an embedded state metric storage, is used for MAP (Maximum A Posterior)-based decoder of turbo codes to reduce the memory requirement of state metric storage. For MAP decoder, this method comprises selecting any state metric from the updated state metrics ... | 10/21/2008 |
| 7433429 | De-interleaver method and system In one embodiment, interleaved signals in a receiver are accessed by memory pointers and delivered to data stream locations without the need to transfer data to an intermediate physical buffer. ... | 10/07/2008 |
| 7434148 | Track buffer in a parallel decoder A method (700) and apparatus (600) are described for performing 2M−1 parallel ACS operations to generate 2M path metric outputs and buffering the 2M path metric outputs in connection with a track buffer (112) i... | 10/07/2008 |
| 7434134 | System and method for trellis decoding in a multi-pair transceiver system A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signa... | 10/07/2008 |
| 7434136 | Method of and apparatus for reading recording medium, harddisk controller An ECC determining unit determines whether an error detected by using an ECC has been corrected. When the detected error has not been corrected, an equalizer output sequence transfer unit transfers an equalizer output sequence yk stored in an equalizer ou... | 10/07/2008 |
| 7434149 | Prediction device and method applied in a Viterbi decoder A prediction device and method for use in a Viterbi decoder is provided. The prediction device is applicable to a communication system with low bit error rate for reducing the count of accessing path memories, thereby lowering the power consumption of the system. Th... | 10/07/2008 |
