Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 7013116 | MIMO systems having a channel decoder matched to a MIMO detector A method and apparatus for reducing the number of erred bits in the decoded signal by using a channel decoder whose transfer characteristic is matched to the transfer characteristic of the MIMO detector. This means that the curve of the transfer characteristic of th... | 03/14/2006 |
| 7010029 | Equalization of transmit diversity space-time coded signals A method executed in a receiver that combines a decoder with an equalizer in a single module, comprising receiving at time k a signal r(k) in the receiver. Selecting as a signal transmitted by a transmitter a signal that minimizes the following equation metric | 03/07/2006 |
| 7010001 | Method and apparatus for supporting adaptive multi-rate (AMR) data in a CDMA communication system Techniques to support adaptive multi-rate (AMR) coded data in a cdma2000 communication system. A number of AMR modes are defined for speech information (of various rates), silence descriptor (SID) (of various types), and blank frame. The speech and SID data are prov... | 03/07/2006 |
| 7006578 | Constellation mapping for modulated communications Constellations (22) arranged in a concentric circle pattern provide simplified control of modulated communication. A plurality of concentric circles (26, 28, 30) with defined points (24) include convolutionally coded and uncoded bits. Constellat... | 02/28/2006 |
| 7007223 | Efficient method and apparatus for low latency forward error correction A method and apparatus for low latency Forward Error Correction (FEC) is described. The low latency FEC can be implemented utilizing shift registers, at least one Linear Feedback Shift Register (LFSR), and a local reference table. ... | 02/28/2006 |
| 7006564 | Adaptive equalizer An adaptive equalizer processes an input signal that includes noise, pre-cursor intersymbol interference, and post-cursor intersymbol interference. The adaptive equalizer includes a feedforward filter which reduces the pre-cursor intersymbol interference and whitens... | 02/28/2006 |
| 7003045 | Method and apparatus for error correction A convolutional encoder (112) comprises a controller (201), having a transmission rate (e.g. frame rate) as an input. The controller (201) initializes the encoder (112) to an initial state based on a transmission rate currently being util... | 02/21/2006 |
| 7002492 | High rate running digital sum-restricted code A method and apparatus are provided for encoding successive data words into respective code words. Each data word is mapped into data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a f... | 02/21/2006 |
| 7002889 | Data reproduction method and apparatus In a data reproduction method and apparatus of the present invention, a Viterbi detection unit is provided, the Viterbi detection unit having a plurality of detectors each providing a first partial response signal with a first constraint length from a first sequence... | 02/21/2006 |
| 7003041 | Device and method for decoding turbo codes A method and apparatus for decoding turbo codes using a sliding window method is disclosed. In decoding a received sequence using a Maximum A Posteriori (MAP) algorithm, a learning by a backward processing is performed for a predetermined length and first resultant ... | 02/21/2006 |
| 7003055 | Systolic equalizer and method of using same A method and apparatus provide a systolic equalizer for Viterbi equalization of an 8-PSK signal distorted by passage through a communication channel. The systolic equalizer architecture is scalable to process, as examples, four, eight and 16 state received signals. ... | 02/21/2006 |
| 7003718 | Memory-based shuffle-exchange traceback for gigabit Ethernet transceiver A decoder having a memory structure which receives and stores potential symbols, with each of the potential symbols having a unique pointer associated therewith. One of the potential symbols is a most likely symbol. The most likely symbol is selected using a pointer... | 02/21/2006 |
| 7000175 | Method and apparatus for pipelined joint equalization and decoding for gigabit communications A method and apparatus for the implementation of reduced state sequence estimation is disclosed that uses precomputation (look-ahead) to increase throughput, with only a linear increase in hardware complexity with respect to the look-ahead depth. The present inventi... | 02/14/2006 |
| 7000177 | Parity check matrix and method of forming thereof A data transmission system is provided for transmitting user data to and receiving data from a communication channel, including a parity check matrix having M tiers, wherein M≦2, Dmin=2*M for M=1 . . . 3 or 2*M≦Dmin≦6 for M>3, wherein Dmin is the minimum Hammi... | 02/14/2006 |
| 6999521 | Method and apparatus for shortening the critical path of reduced complexity sequence estimation techniques A method and apparatus are disclosed for improving the processing time of reduced complexity sequence estimation techniques, such as reduced state sequence estimation. Precomputing the branch metrics for all possible symbol combinations in the channel memory makes i... | 02/14/2006 |
| 6999532 | Decoding circuit and method of Viterbi decoder The invention provides a decoding circuit and a decoding method of a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller... | 02/14/2006 |
| 6999530 | Using SISO decoder feedback to produce symbol probabilities for use in wireless communications that utilize turbo coding and transmit diversity In a wireless communication receiver (31) of a wireless communication system that utilizes transmit diversity and turbo coding, symbol probabilities (45, 46) are generated (34) based at least in part on a posteriori output probabilities (47, ... | 02/14/2006 |
| 6999531 | Soft-decision decoding of convolutionally encoded codeword A method and apparatus for decoding convolutional codes used in error-correcting circuitry for digital data communication. To increase the speed and precision of the decoding process, the branch and/or state metrics are normalized during the soft decision calculatio... | 02/14/2006 |
| 6999503 | Partial response signaling for orthogonal frequency division multiplexing The system includes a transmitter for generating a signal and a cyclic prefix, wherein the transmitter suppresses a plurality of sub-symbols of the signal to produce a partial response signal. A portion of the partial response signal is dropped and the resulting tru... | 02/14/2006 |
| 6993704 | Concurrent memory control for turbo decoders The concurrent memory control turbo decoder solution of this invention uses a single port main memory and a simplified scratch memory. This approach uses an interleaved forward-reverse addressing which greatly relieves the amount of memory required. This approach is... | 01/31/2006 |
| 6993703 | Decoder and decoding method A decoder for performing log-sum corrections by means of a linear approximation, putting stress on speed, with a reduced circuit dimension without adversely affecting the decoding performance of the circuit. The decoder includes a linear approximation circuit that c... | 01/31/2006 |
| 6993702 | Radix-N architecture for deinterleaver-depuncturer block A de-interleaver-de-puncturer architecture is scalable and capable of achieving a higher data throughput than that achievable using a conventional disjointed de-interleaver-de-puncturer architecture. The higher data throughput is achieved without increasing the cloc... | 01/31/2006 |
| 6993464 | Optimized filter parameters design for digital IF programmable downconverter The present invention discloses a method for finding an optimized filter parameters design to meet input specifications and hardware constraints in accordance with a typical single channel digital IF programmable downconverter. Said typical single channel digital IF... | 01/31/2006 |
| 6993699 | Turbo decoding apparatus and interleave-deinterleave apparatus In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and dat... | 01/31/2006 |
| 6986000 | Interleaving apparatus and deinterleaving apparatus A signal record reproduction device 1 of the invention comprises a microcomputer 12 and a memory 17. A series of data blocks are divided into a plurality of items of element data. The element data is interleaved and stored to the memory 17. | 01/10/2006 |
| 6980602 | Normalization of equalizer soft output for channels with varying noise power An apparatus for and method of generating normalized soft decision information output from an inner decoder (i.e. equalizer) in a communications receiver. The invention is operative to normalize the soft decision information before it enters a soft outer decoder. Th... | 12/27/2005 |
| 6980140 | Flash ADC receiver with reduced errors Symbol decoding errors at a receiver utilising a flash analog to digital converter (ADC) can be reduced by adjusting a reference voltage level of the ADC where a decoding error rate at the reference voltage level exceeds a threshold. ... | 12/27/2005 |
| 6980607 | Method for decoding a data signal A turbo decoder is used in a method for blockwise decoding a data signal that is error protection coded at a transmitter and that is detected in a receiver. The turbo decoder includes two feedback symbol estimators. In order to calculate its output values, at least ... | 12/27/2005 |
| 6981203 | Method and apparatus for random shuffled turbo multiuser detector A multi-user turbo decoder combining multi-user detection and forward error correction decoding is disclosed in which randomly ordered indices are assigned to interfering users before a decoding tree is constructed in the multi-user decoder for each symbol interval ... | 12/27/2005 |
| 6975692 | Scaling of demodulated data in an interleaver memory In a method of demodulating and decoding an encoded interleaved signal, a received encoded interleaved signal is demodulated, thereby producing soft-decision demodulated output words. Thereafter, the soft-decision demodulated output words are de-interleaved and scal... | 12/13/2005 |
| 6973615 | System of and method for decoding trellis codes Systems and related methods are described for (1) determining one or more state probabilities for one or more states in a trellis representation; (2) determining an estimate of or extrinsic output for a bit using a trellis representation; (3) performing a MAX* 2−>... | 12/06/2005 |
| 6970520 | Methods and systems for accumulating metrics generated by a sequence estimation algorithm Radiocommunication systems, methods and terminals are described wherein metrics associated with MLSE detecting techniques, e.g., using the Viterbi algorithm, are accumulated in a manner which is less computationally intensive than conventional techniques. The delta ... | 11/29/2005 |
| 6970522 | Data retrieval A digital data storage (DDS) system for reading DDS tapes employs a partial response maximum likelihood detection system which utilises redundancy in the 8-10 DC free modulation encoding to reduce low frequency noise. The system incorporates a time-varying trellis d... | 11/29/2005 |
| 6968495 | Super high speed viterbi decoder using circularly connected 2-dimensional analog processing cell array A super high speed Viterbi decoder and decoding method with a circularly connected 2-dimensional analog processing cell array. The Viterbi decoder has a 2-dimensional parallel processing structure, in which analog processing cells are located at nodes of a trellis d... | 11/22/2005 |
| 6968533 | Process description apparatus and method, and process classification method A process is described based on activities and dependence relationship between the activities. The dependence relationship is described based on resource and coordination method. An epistemological ground is set corresponding to the domain of the process and other c... | 11/22/2005 |
| 6963962 | Memory system for supporting multiple parallel accesses at very high frequencies A memory system for operation with a processor, such as a digital signal processor, includes a high speed pipelined memory, a store buffer for holding store access requests from the processor, a load buffer for holding load access requests from the processor, and a ... | 11/08/2005 |
| 6963296 | Recording method, recording apparatus, transmitting apparatus, reproducing method, reproducing apparatus, receiving apparatus, recording medium, and transmission medium There is disclosed a recording method for performing a DSV control while recording a recording signal generated by inserting a synchronous signal for decoding reproduction data into every predetermined number of code words in a code word string satisfying a predeter... | 11/08/2005 |
| 6961391 | Signal processor used for symbol recovery and methods therein A signal processor and method therein that is arranged and constructed to recover a sequence of symbols from a received signal is discussed. The processor includes a symbol selector for selecting a symbol based on the received signal over a time period including pre... | 11/01/2005 |
| 6961010 | DC-free code design with increased distance between code words A method and apparatus are provided for encoding digital information. A sequence of successive data words are encoded into a sequence of successive code words according to a code, such that a running digital sum (RDS) of the sequence of successive code words is boun... | 11/01/2005 |
| 6961921 | Pipeline architecture for maximum a posteriori (MAP) decoders The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for the first sliding window of the decoder, the reverse metrics for each window are calcul... | 11/01/2005 |
