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| Number | Title | Issue Date |
| 8156411 | Error correction of an encoded message An encoded message is stored in a first memory. The encoded message is retrieved from the first memory as a retrieved encoded message that may contain an error. Syndromes are generated from the retrieved encoded message. The syndromes are used to determine if the re... | 04/10/2012 |
| 8151173 | Semiconductor storage device comprising memory array including normal array and parity array Data latches, multiplexers, an ECC circuit section, and an input/output circuit section are arranged in columns and adjacent to each other, in an extending direction of data lines that are formed in a direction orthogonal to word lines. A layout of a data path syste... | 04/03/2012 |
| 8140945 | Hard component failure detection and correction In one embodiment, a memory controller comprises a check bit encoder circuit coupled to receive a data block to be written to memory, a check/correct circuit coupled to receive an encoded data block read from the memory, and a hard failure detection circuit coupled ... | 03/20/2012 |
| 8127211 | Adding known data to CRC processing without increased processing time Cyclic redundancy check processing is applied advantageously to a set of input data that includes an unknown data portion and a data portion that is already known before the unknown data portion becomes available. A syndrome contribution that the already-known data ... | 02/28/2012 |
| 8127213 | Method, system, and apparatus for adjacent-symbol error correction and detection code A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases. In an embodiment, a set of m bits of a first symbol and a set of m bits of a second symbol from a first set of data for transm... | 02/28/2012 |
| 8127212 | System and method for determining the fault-tolerance of an erasure code A method for determining a fault tolerance of an erasure code includes deriving base erasure patterns from a generator matrix of an erasure code, determining which of the base erasure patterns are adjacent to one another and XORing the adjacent base erasure patterns... | 02/28/2012 |
| 8122329 | Methods of operating memory devices using error correction and rereading techniques Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a b... | 02/21/2012 |
| 8117521 | Implementation of recycling unused ECC parity bits during flash memory programming Methods for recycling unused error correction code (ECC) during flash memory programming, comprise generating ECC from user data to form a syndrome and storing the syndrome into volatile memory. ECC is re-encoded corresponding to the syndrome read from the memory wi... | 02/14/2012 |
| 8112696 | Apparatus for providing error correction capability to longitudinal position data A method and apparatus for providing error correction capability to longitudinal position data are disclosed. Initially, data are encoded via a set of even LPOS words and a set of odd LPOS words. The encoded data are then decoded by generating a set of syndrome bits... | 02/07/2012 |
| 8086941 | Computing an error detection code syndrome based on a correction pattern The present invention is all error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of dat... | 12/27/2011 |
| 8078947 | Data processing circuit and method A data processing method is provided. Target page data are read from a memory cell array and addresses of multiple programmed-error bits are stored. A first syndrome polynomial and a second syndrome polynomial are obtained according to the target page data, and the ... | 12/13/2011 |
| 8074154 | Methods and apparatus for encoding and decoding cyclic codes by processing multiple symbols per cycle Provided are an encoder and a syndrome computer for cyclic codes which process M codeword symbols per cycle where M is greater than or equal to one, whereby the encoder and syndrome computer optionally further provide the configurability of a different M value for e... | 12/06/2011 |
| 8055985 | Decoding method and decoding circuit An approach to dividing syndrome calculations into two steps and serially processing them requires a long time for the syndrome calculations with respect to an entire decoding process. Therefore, there is disclosed an error correction decoding circuit for a playing ... | 11/08/2011 |
| 8055984 | Forward error correction scheme compatible with the bit error spreading of a scrambler A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects... | 11/08/2011 |
| 8028221 | Error correction and error detection method for reading of stored information data and a storage control unit for the same An error correction and/or error detection method reads of stored information data from a storage device; wherein in addition to the information data, code data is read from the storage device. Syndrome data is formed from the information data and the code data in o... | 09/27/2011 |
| 8024645 | Method for error detection in a decoded digital signal stream The present invention relates to a method for analyzing a decoded digital signal stream. The method comprises decoding an encoded digital signal stream to obtain a decoded digital stream and terminating the decoding operation in an N dimension, wherein N is an integ... | 09/20/2011 |
| 8001449 | Syndrome-error mapping method for decoding linear and cyclic codes A decoding method is presented for error-correcting codes based on the syndrome decoding scheme, which means the set of all syndromes is one-to-one corresponding to the set of all correctable error patterns. The improvement in the high-speed error-correcting capabil... | 08/16/2011 |
| 8001450 | Semiconductor memory device capable of changing ECC code length The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side... | 08/16/2011 |
| 7996748 | ECC for single 4-bits symbol correction of 32 symbols words with 22 maximum row weight matrix An error correction device is provided. Such error correction device may make use of an error-correction code defined by a parity matrix specialized for the application to multilevel memories. For example, the parity matrix is characterized by having a Maximum Row W... | 08/09/2011 |
| 7971130 | Multi-level signal memory with LDPC and interleaving Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell ada... | 06/28/2011 |
| 7962839 | Single burst error correction Identifying a burst error is disclosed. Identifying includes computing a syndrome check polynomial corresponding to a burst of length up to 2t−1 in received data and identifying a shortest burst based on the longest consecutive root sequence of the syndrome check ... | 06/14/2011 |
| 7949931 | Systems and methods for error detection in a memory system A method for error detection in a memory system. The method includes calculating one or more signatures associated with data that contains an error. It is determined if the error is a potential correctable error. If the error is a potential correctable error, then t... | 05/24/2011 |
| 7941734 | Method and apparatus for decoding shortened BCH codes or reed-solomon codes The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error loc... | 05/10/2011 |
| 7925962 | DVB-H system and method for performing forward error correction A Digitally Video Broadcasting—Handheld (DVB-H) system for performing forward error correction includes: a tuner for receiving a data stream; a base-band receiver, coupled to the tuner, for extracting data bytes of a multi-protocol-encapsulation forward-error-corr... | 04/12/2011 |
| 7844886 | Parallel processing error detection and location circuitry for configuration random-access memory Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. ... | 11/30/2010 |
| 7840883 | DVB-H receiver for forward error correction and method thereof A DVB-H receiver for performing forward error correction is disclosed. The DVB-H receiver includes: a tuner, for receiving a data stream; a base-band receiver, coupled to the tuner, for continuously extracting and transmitting data bytes of an MPE-FEC frame from the... | 11/23/2010 |
| 7797614 | Non-redundant multi-error correcting binary differential demodulator An algorithm for a non-redundant multi-error correcting binary differential demodulator simplifies error detection and reduces memory requirements in circuits embodying the same. The demodulator includes a differential detectors (DD) module, an error signal generato... | 09/14/2010 |
| 7752529 | Combined LDPC (low density parity check) encoder and syndrome checker Combined LDPC (Low Density Parity Check) encoder and syndrome checker. A novel approach is presented by which the encoding processing and at least a portion of the decoding processing of an LDPC coded signal can be performed using a shared circuitry. The LDPC encodi... | 07/06/2010 |
| 7743311 | Combined encoder/syndrome generator with reduced delay A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or m... | 06/22/2010 |
| 7694209 | Decoding device for decoding codeword According to one embodiment, a decoding device decodes a (k+m) bit codeword in accordance with a check matrix. The codeword includes k-bit information symbols and an m-bit parity check code. The check matrix includes a unit matrix and a coefficient matrix. The most ... | 04/06/2010 |
| 7689894 | Decoding apparatus and method therefor A decoding apparatus adapted for an optical access system comprises an interface, a detection element, and an error correction element. The interface receives a data from an optical storage medium. The detection element executes an error detection on the data receiv... | 03/30/2010 |
| 7689895 | On-the fly error checking and correction CODEC system and method for supporting non-volatile memory An on-the-fly error checking and correcting system and method of supporting a non-volatile memory processes data using an on-the-fly error correction method to be performed between a temporary memory and a flash memory. The flash memory stores actual data read from ... | 03/30/2010 |
| 7681110 | Decoding technique for linear block codes The present decoding technique provides an efficient technique for decoding linear block codes from multiple encoders. When an error in a code sequence is detected, the decoding technique estimates a confidence for each bit within the code sequence. Based on the con... | 03/16/2010 |
| 7653867 | Multi-source data encoding, transmission and decoding using Slepian-Wolf codes based on channel code partitioning System and method for Slepian-Wolf coding using channel code partitioning. A generator matrix is partitioned to generate multiple sub-matrices corresponding respectively to multiple correlated data sources. The partitioning is in accordance with a rate allocation am... | 01/26/2010 |
| 7620879 | Method of detecting occurrence of error event in data and apparatus for the same A method of detecting an occurrence of an error event in data and an apparatus for the same are provided. The method includes: preparing an error detection code wherein syndrome sequences for dominant error events are all different; generating a codeword from source... | 11/17/2009 |
| 7607071 | Error correction using iterating generation of data syndrome An embodiment of the present invention is a technique to perform error correction using a trial-and-error method. A syndrome generator provides a generation of a data syndrome of a data word modified according to a selection of at least one of error correcting param... | 10/20/2009 |
| 7600177 | Delta syndrome based iterative Reed-Solomon product code decoder A method for generating syndromes for a data block is disclosed. The method generally includes the steps of (A) calculating a plurality of row syndromes and a plurality of column syndromes for the data block arranged as a Reed-Solomon product code, (B) storing only ... | 10/06/2009 |
| 7590924 | Architecture and control of Reed-Solomon list decoding Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be org... | 09/15/2009 |
| 7587658 | ECC encoding for uncorrectable errors An error detecting and correcting method and mechanism. An error correcting code for data is utilized wherein a special syndrome pattern is used to indicate corresponding data includes a previously detected uncorrectable error. In response to receiving data and corr... | 09/08/2009 |
| 7562283 | Systems and methods for error correction using binary coded hexidecimal or hamming decoding Systems and methods for error correction of data. In one embodiment of the invention, a plurality of error correction schemes are applied when encoding data and depending on the circumstances, one or more of those schemes is selected to decode the data. In one of th... | 07/14/2009 |
