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| Number | Title | Issue Date |
| 8136020 | Forward error correction CODEC A present invention discloses a method for performing forward error correction (FEC) in long-haul submarine transmission systems. Data is encoded at a transmitter by serially concatenated, binary Bose-Ray-Chaudhuri-Hocquenghem (BCH) error correcting codes. The inven... | 03/13/2012 |
| 8132081 | Binary BCH decoders Binary Bose-Chaudhuri-Hocquenghem (BCH) encoded data is processed by obtaining a set of syndromes associated with the binary BCH encoded data, including a subset of odd-term syndromes and a subset of even-term syndromes. During initialization of a variant error-loca... | 03/06/2012 |
| 8122328 | Bose-Chaudhuri-Hocquenghem error correction method and circuit for checking error using error correction encoder A Bose-Chaudhuri-Hocquenghem (BCH) error correction circuit and method including storing normal data and first parity data in a memory cell array, the normal data and first parity data forming BCH encoded data; generating second parity data from the stored normal da... | 02/21/2012 |
| 8006171 | Apparatus for random parity check and correction with BCH code An apparatus for random parity check and correction with BCH code is provided, including a Bose-Chaudhuri-Hocquenghem (BCH) parity check code encoder, a channel, a BCH parity check code decoder, and a static random access memory (SRAM). The BCH parity check code enc... | 08/23/2011 |
| 7908543 | Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS−1) to generate a first recovered string (S1), and performin... | 03/15/2011 |
| 7890843 | Semiconductor memory device A memory device includes an error detection and correction system with an error correcting code over Galois field GF(2n), which has an operation circuit configured to execute addition/subtraction with modulo 2n−1, wherein the operation circui... | 02/15/2011 |
| 7865809 | Data error detection and correction in non-volatile memory devices Data error detection and correction in non-volatile memory devices are disclosed. Data error detection and correction can be performed with software, hardware or a combination of both. Generally an error corrector is referred to as an ECC (error correction code). On... | 01/04/2011 |
| 7823050 | Low area architecture in BCH decoder An improvement to a key equation solver block for a BCH decoder, where the key equation solver block having a number of multiplier units specified by X, where: t*(7*t−1)/(codeword_len−3)≦X | 10/26/2010 |
| 7774688 | Hardware efficient decoding system for Bose, Ray-Chaudhuri, Hocquenghem (BCH) product codes A decoder that decodes Bose, Ray-Chaudhuri, Hocquenghem (BCH) codewords includes an inner decoding module that decodes inner codes of two dimensional BCH product codewords and that includes an error decoding module that computes error values, an outer decoding modul... | 08/10/2010 |
| 7694207 | Method of decoding signals having binary BCH codes A method of correcting a communication signal with BCH product codes is disclosed. The method comprising the steps of receiving a codeword vector, establishing a generator polynomial, establishing a check polynomial, calculating a binary-matrix, and calculating the ... | 04/06/2010 |
| 7647545 | Signal and protocol for remote dog trainer signaling with a forward error correction A transmitter for a dog training system, the transmitter having a command input device for inputting a training command input into the transmitter, and a transmitter controller connected to the command input device. The transmitter controller translates the training... | 01/12/2010 |
| 7509564 | High speed syndrome-based FEC encoder and system using same A decoder, encoder and corresponding system are disclosed for providing fast Forward Error Correcting (FEC) decoding and encoding of syndrome-based error correcting codes. Three-parallel processing is performed by elements of the system. More particularly, in an ill... | 03/24/2009 |
| 7484165 | Forward error correction coding A forward error correcton coding method comprises a generalized concatenated code comprising a plurality of outer component codes and a plurality of inner component codes. The outer components codes comprise Reed-Solomon codes and a plurality of binary codes of equa... | 01/27/2009 |
| 7458007 | Error correction structures and methods A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier. ... | 11/25/2008 |
| 7440475 | Error-correction multiplexing apparatus, error-correction demultiplexing apparatus, optical transmission system using them, and error-correction multiplexing transmission method A first demultiplexer and a second demultiplexer receive and demultiplex STM-64 data to generate parallel data. A FEC frame generating encoder carries out error correction encoding operation in a column direction of the parallel data that constitutes a matrix, adds ... | 10/21/2008 |
| 7437653 | Erased sector detection mechanisms The present invention presents a non-volatile memory and method for its operation that allows instant and accurate detection of erased sectors when the sectors contain a low number of zero bits, due to malfunctioning cells or other problems, and the sector can still... | 10/14/2008 |
| 7434139 | Remote module for a communications network Determination of the location of an error condition or a failure includes receiving at a network interface a first framed digital signal from customer premises equipment, and determining whether the first framed digital signal indicates a failure. Overhead bits are ... | 10/07/2008 |
| 7424662 | Method and system for providing low density parity check (LDPC) encoding An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The informati... | 09/09/2008 |
| 7421642 | Method and apparatus for error detection The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data... | 09/02/2008 |
| 7380195 | Error correction using error detection codes A method, apparatus, and computer-readable media comprises receiving a detected sequence representing a signal on a channel, wherein the detected sequence comprises data bits and one or more error detection code bits; receiving one or more error indications for the ... | 05/27/2008 |
| 7372652 | Correcting errors in disk drive read back signals by iterating with the Reed-Solomon decoder A read channel includes a signal receiver that receives a read back signal and a signal detector to detect symbols in the read back signal. The signal detector includes a first detector that generates raw decisions as a function of the read back signal, a post proce... | 05/13/2008 |
| 7356076 | System and method supporting auto-recovery in a transceiver system A method and apparatus are disclosed to aid a transceiver chip, in a serial data communications system, in recovering from a system-side, out-bound data clocking problem. If a problem with a primary clock signal, used to clock data from a system-side of a transceive... | 04/08/2008 |
| 7353303 | Time slot memory management in a switch having back end memories stored equal-size frame portions in stripes A switch comprising front-end and back-end application specific integrated circuits (ASICs) is disclosed. Frame storage and retrieval in the switch is achieved by dividing a frame into equal sized portions that are sequentially stored in switch memory during an assi... | 04/01/2008 |
| 7346834 | Randomizer systems for producing multiple-symbol randomizing sequences A system that produces one or more non-repeating randomizer sequences of up to 2m−1 or more m-bit symbols includes a randomizer circuit that is set up in accordance with a polynomial with primitive elements of GF(2m) as coefficients. The syst... | 03/18/2008 |
| 7328397 | Method for performing error corrections of digital information codified as a symbol sequence A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incor... | 02/05/2008 |
| 7328395 | Iterative Reed-Solomon error-correction decoding Systems and methods are provided to correct errors occurring in a decision-codeword that is generated by a detector. A decoder determines whether errors in the decision-codeword are of a degree that exceeds the correction capability of a Reed-Solomon error-correctio... | 02/05/2008 |
| 7321600 | System, method, and article of manufacture for initializing a communication link using GFP data frames A system and a method for initializing a communication link for transmitting a data stream from a first computer through a synchronous optical communication network to a second computer are provided. The method includes transmitting a first request message in a firs... | 01/22/2008 |
| 7320114 | Method and system for verification of soft error handling with application to CMT processors A method provides for verifying soft error handling in an integrated circuit (IC) design. A diagnostic program is executed on a virtual IC based on the IC design using a simulator. A soft error is injected into the virtual IC to trigger hardware error correction in ... | 01/15/2008 |
| 7313742 | Logic circuitry having self-test function A logic circuit having a self-test function includes a plurality of F/Fs having at least first-, second- and last-stage scanning F/Fs, each having a clock input, a scanning input and a scanning output terminals. The scanning F/Fs are connected one another so as to s... | 12/25/2007 |
| 7313583 | Galois field arithmetic unit for use within a processor A Galois field arithmetic unit includes a Galois field multiplier section and a Galois field adder section. The Galois field multiplier section includes a plurality of Galois field multiplier arrays that perform a Galois field multiplication by multiplying, in accor... | 12/25/2007 |
| 7310767 | Decoding block codes A method and structure of processing soft information in a block code decoder, includes a soft-input soft-output decoder receiving a length n soft input vector, creating a binary vector Y corresponding to the soft input vector, hard decoding each linear function Xi ... | 12/18/2007 |
| 7302631 | Low overhead coding techniques A low overhead coding technique is disclosed. In one particular exemplary embodiment, the low overhead coding technique may be realized as a method for coding information comprising receiving a block of information, and encoding the block of information such that a ... | 11/27/2007 |
| 7296216 | Stopping and/or reducing oscillations in low density parity check (LDPC) decoding Stopping or reducing oscillations in Low Density Parity Check (LDPC) codes. A novel solution is presented that completely eliminates and/or substantially reduces the oscillations that are oftentimes encountered with the various iterative decoding approaches that are... | 11/13/2007 |
| 7292603 | Memory-efficient conversion between differing data transport formats of SONET overhead data In a SONET apparatus, the data flow differences between OC-768 and OC-192 can be exploited to effectuate conversion between OC-768 and OC-192 using as little as 256 bytes of memory. ... | 11/06/2007 |
| 7284184 | Forward error correction scheme compatible with the bit error spreading of a scrambler A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects... | 10/16/2007 |
| 7275198 | Apparatus and method for transmitting/receiving error detection information in a communication system Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the n... | 09/25/2007 |
| 7272195 | Method and circuit for controlling the peak power of a filtered signal in a single carrier data transmission system Disclosed is a method for controlling the peak power of a filtered signal in a single carrier data transmission system. The method comprises the steps of receiving a digital sequence (13) from a data source; generating a new digital sequence (a(k)); shaping f... | 09/18/2007 |
| 7266749 | Trellis construction based on parity check matrix for BCH code A method for constructing a simplified trellis diagram for BCH-encoded information is disclosed. BCH-encoded information is received, having a corresponding parity check matrix H. The parity check matrix H is expressed as an ordered sequence of columns of matrices. ... | 09/04/2007 |
| 7263617 | Method and system for detecting a security violation using an error correction code A system and method for detecting a security violation using an error correction code. Some illustrative embodiments may be a method used in a computing system comprising reading a codeword comprising data and an error correction code (ECC) (the ECC associated with ... | 08/28/2007 |
| 7263646 | Method and apparatus for skew compensation A method that measures a skew between a data signal and a clock signal at a receiving end of a serial link and then adjusts a phase relationship between the data signal and the clock signal to reduce the skew. ... | 08/28/2007 |
