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| Number | Title | Issue Date |
| 8185806 | EDC generating circuit and EDC generating method correcting EDC generated from main data according to header An EDC generating circuit includes a memory unit, an EDC generating module, a header generator and an EDC correcting circuit. The EDC generating module, which is coupled to the memory unit, is used for generating a first EDC according to at least one main data, and ... | 05/22/2012 |
| 8185807 | Method and apparatus of encoding and decoding data using low density parity check code in a wireless communication system A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plur... | 05/22/2012 |
| 8176393 | Encoding device for error correction, encoding method for error correction and encoding program for error correction The present invention aims at providing an encoding device for error correction, encoding method for error correction and encoding program for error correction wherein countermeasures against eavesdropping are taken into account. To achieve this, in accordance with ... | 05/08/2012 |
| 8176394 | Linear feedback shift register structure and method An LFSR module is configured according to a characteristic polynomial for generating an output stream according to an input stream. The LFSR module has several LFSRs coupled together and an output generator. Each LFSR respectively receives a sub-input stream and at ... | 05/08/2012 |
| 8166376 | Techniques for correcting errors and erasures using a single-shot generalized minimum distance key equation solver A system corrects errors in a codeword. The system includes a channel that sorts reliability numbers of symbols in the codeword to create an ordered list of candidate erasure locations. The system also includes a generalized minimum distance decoder that iteratively... | 04/24/2012 |
| 8161360 | Integrated interleaved codes Integrated interleaved encoding is performed by obtaining a first piece of input data and a second piece of input data. The first piece of input data is systematically encoded using a first generator polynomial to obtain a first codeword. A second codeword is genera... | 04/17/2012 |
| 8161359 | System and method for generating a cyclic redundancy check A cyclic redundancy check generator includes a plurality of shift registers, each shift register corresponding to a coefficient of a general polynomial key word. A plurality of programmable registers are programmed based on a specific polynomial key word. The specif... | 04/17/2012 |
| 8156410 | Fast debugging tool for CRC insertion in MPEG-2 video decoder A video decoder capable of generating a check data in response to a data selection code for debugging is disclosed. The video decoder includes a plurality of functional blocks, wherein each said plurality of functional blocks has a output signal to be used as an inp... | 04/10/2012 |
| 8117520 | Error detection for multi-bit memory Systems, methods, and devices are disclosed, including a device that includes a plurality of data locations, a quantizing circuit coupled to the plurality of data locations, and an error detection module coupled to the quantizing circuit. In some embodiments, the er... | 02/14/2012 |
| 8112695 | Method for encoding data message K' for transmission from sending station to receiving station as well as method for decoding, sending station, receiving station and software Irregular LDPC codes have a construction which allows one to obtain a number of codes with different length from a single prototype code with a parity check matrix given by H=[Hz Hi], where Hz specifies the well-known zigzag pattern in the corresponding Tanner graph... | 02/07/2012 |
| 8108759 | Error detection and correction using error pattern correcting codes In general, the disclosure describes techniques for detecting and correcting single or multiple occurrences of data error patterns. This disclosure discusses the generation and application of high-rate error-pattern-correcting codes to correct single instances of ta... | 01/31/2012 |
| 8108760 | Decoding of linear codes with parity check matrix A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of ... | 01/31/2012 |
| 8099655 | Galois field multiplier system and method A Galois Field multiplier circuit for multiplying two polynomials (multiplicands). The multiplier circuit can use any arbitrary primitive polynomial to preserve the Galois Field. The multiplier circuit includes at least one logic unit that receives as a first input ... | 01/17/2012 |
| 8078944 | Systems, methods and computer program products including features for coding and/or recovering data Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data streams from W data input streams produced from input data. Moreover, the method may include generating the H discrete outp... | 12/13/2011 |
| 8078943 | Error correction code for correcting shift and additive errors An error correction system is disclosed comprising an encoder operable to generate an encoded codeword of a polynomial code over a Galois field GF(q) comprising q elements, wherein the encoded codeword comprises an input data sequence, at least one check symbol, and... | 12/13/2011 |
| 8074150 | Multi-layer cyclic redundancy check code in wireless communication system A wireless communication device includes a receiver configured to receive a transport block with a sequence of bits wherein A is the number of bits, a first cyclic redundancy check (CRC) coder configured to generate a first block of CRC parity bits on a transport bl... | 12/06/2011 |
| 8065592 | Multi-source data encoding, transmission and decoding using slepian-wolf codes based on channel code partitioning System and method for designing Slepian-Wolf codes by channel code partitioning. A generator matrix is partitioned to generate a plurality of sub-matrices corresponding respectively to a plurality of correlated data sources. The partitioning is performed in accordan... | 11/22/2011 |
| 8042025 | Determining a message residue In one aspect, circuitry to determine a modular remainder with respect to a polynomial of a message comprised of a series of segment. In another aspect, circuitry to access at least a portion of a first number having a first endian format, determine a second number ... | 10/18/2011 |
| 8032817 | Error detection and location circuitry for configuration random-access memory Error detection and error location determination circuitry is provided for detecting and locating soft errors in random-access-memory arrays on programmable integrated circuits. The random-access-memory arrays contain rows and columns of random-access-memory cells. ... | 10/04/2011 |
| 8028220 | Method of determining coordinate values of a position on a printed document with respect to a plurality of patterns printed on the document A method is disclosed of determining a coordinate value of a position on a printed document having patterns printed thereon. Each pattern represents a sequence having a repeating codeword of a cyclic position code. The method includes sensing the patterns printed on... | 09/27/2011 |
| 8010879 | Error correction method and apparatus for data storage device The present invention provides a data storage device comprising a disk storage medium containing user data in a plurality of sectors, a head for writing or reading the user data and error correcting means for correcting an error that occurs in the user data during t... | 08/30/2011 |
| 8001447 | Error correction method and apparatus for data storage device The present invention provides a data storage device comprising a disk storage medium containing user data in a plurality of sectors, a head for writing or reading the user data and error correcting means for correcting an error that occurs in the user data during t... | 08/16/2011 |
| 8001446 | Pipelined cyclic redundancy check (CRC) Methods and apparatus to provide a pipelined cyclic redundancy check (CRC) are described. In one embodiment, a plurality of stages determines a plurality of CRC values corresponding to portions of a data packet. The plurality of CRC values are accumulated to determi... | 08/16/2011 |
| 7984364 | Apparatus and method for transmitting/receiving signal in communication system An apparatus and method for encoding/decoding a non-binary low density parity check (LDPC) code in a communication system. The apparatus and method includes receiving an information vector; generating a non-binary LDPC code by encoding the information vector into a ... | 07/19/2011 |
| 7979780 | Error correction encoding apparatus and error correction encoding method used therein An error correction encoding apparatus wherein the apparatus structure is simple; an iterative decoding is used to achieve a decoding with a close-to-optimum precision; and a simple mathematical expression is used to perform an evaluation of the characteristic of an... | 07/12/2011 |
| 7962838 | Memory device with an ECC system A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and search... | 06/14/2011 |
| 7962837 | Technique for reducing parity bit-widths for check bit and syndrome generation for data blocks through the use of additional check bits to increase the number of minimum weighted codes in the hamming code H-matrix A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while a... | 06/14/2011 |
| 7962836 | Electronic data flash card with bose, ray-chaudhuri, hocquenghem (BCH) error detection/correction A Bose, Ray-Chaudhuri, Hocquenghem (BCH) decoder is employed in non-volatile memory applications for determining the number of errors and locating the errors in a page of information. The decoder includes a syndrome calculator responsive to a sector of information. ... | 06/14/2011 |
| 7958436 | Performing a cyclic redundancy checksum operation responsive to a user-level instruction In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic red... | 06/07/2011 |
| 7945843 | Error correcting code A system for protecting a codeword u against an error in at least one 1 (q=2r). The code word u includes information symbols u[0] . . . u[k−1] , k>1 , each information symbol representing an in... | 05/17/2011 |
| 7941733 | Semiconductor memory device A memory device includes an error detection and correction system with an error correcting code over GF(2n) wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n−1, and wherein the operation cir... | 05/10/2011 |
| 7913149 | Low complexity LDPC encoding algorithm A method of encoding a binary source message u, by calculating x:=Au, calculating y:=B′x, resolving the equation Dp=y for p, and incorporating u and p to produce an encoded binary message v, where A is a matrix formed only of permutation sub matrices, B′ is a ma... | 03/22/2011 |
| 7913151 | Forward error correction with self-synchronous scramblers Systems and methods correct multiplied errors generated by feedback taps in self-synchronous descramblers. The multiplication of errors degrades the performance of most linear cyclic error check codes. Disclosed techniques are general applicable to multiplied errors... | 03/22/2011 |
| 7913150 | Error detection in a communications link An integrated circuit communications interface operable consistent with multiple data transmission protocols includes error detection circuitry that implements a cyclic redundancy check (i.e., CRC) function. The error detection circuitry generates a checksum based, ... | 03/22/2011 |
| 7904794 | Method of detecting and correcting a prescribed set of error events based on error detecting code A method of constructing an effective generator polynomial for error correction by which a unique set of syndromes for each error event is produced is provided. The method includes preparing a set of dominant error events from the intersymbol interference characteri... | 03/08/2011 |
| 7900121 | Method and device for determining indices assigned to correction symbols A determination of indexes allocated to error correcting symbols is provided. Encoded code symbols are generated by means of a generator matrix of a block code from number of source symbols and the encoded transmission errors occur in the received code symbols, the ... | 03/01/2011 |
| 7890842 | Computer-implemented method for correcting transmission errors using linear programming A computer-implemented method for correcting transmission errors. According to the method, a transmitted vector corrupted by error can be recovered solving a linear program. The method has applications in the transmission of Internet media, Internet telephony, and s... | 02/15/2011 |
| 7886214 | Determining a message residue A description of techniques of determining a modular remainder with respect to a polynomial of a message comprised of a series of segments. An implementation can include repeatedly accessing a strict subset of the segments and transforming the strict subset of segme... | 02/08/2011 |
| 7870466 | Parallel cyclic code generation device and parallel cyclic code error detection device To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unit 53 executes computation of exclusive-OR of a cyclic code R(x) of the integral multiple bit bits block A(x) and a d... | 01/11/2011 |
| 7870467 | Data converter, information recorder, and error detector A data converter includes: an input module to which a first data series is input, the first data series having a first data sequence and a first error detection code corresponding to a remainder of division of the first data sequence by a predetermined polynomial; a... | 01/11/2011 |
