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| Number | Title | Issue Date |
| 8190974 | Error detection and correction for external DRAM One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and rela... | 05/29/2012 |
| 8166371 | Semiconductor memory system and signal processing system A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring ... | 04/24/2012 |
| 8136017 | Multi-layer semiconductor memory device comprising error checking and correction (ECC) engine and related ECC method Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell arr... | 03/13/2012 |
| 8099652 | Non-volatile memory and methods with reading soft bits in non uniform schemes A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference th... | 01/17/2012 |
| 8091010 | Error correction circuit and method for reducing miscorrection probability and semiconductor memory device including the circuit An error correction circuit and method for reducing a miscorrection probability and a semiconductor memory device including the circuit are provided. The error correction circuit includes an error check and correction (ECC) encoder and an ECC decoder. The ECC encode... | 01/03/2012 |
| 8078942 | Register error correction of speculative data in an out-of-order processor In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first er... | 12/13/2011 |
| 8078941 | Memory system, memory system controller, and a data processing method in a host apparatus A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error cor... | 12/13/2011 |
| 8055979 | Flash memory with coding and signal processing A solid state non-volatile memory unit includes, in part, an encoder, a multi-level solid state non-volatile memory array adapted to store data encoded by the encoder, and a decoder adapted to decode the data retrieved from the memory array. The memory array may be ... | 11/08/2011 |
| 8015473 | Method, system, and apparatus for ECC protection of small data structures Data structures of different sizes may be stored in memory using different ECC schemes. A memory device may include multiple ECC engines to support error correction operations on different sized data structures. ... | 09/06/2011 |
| 8010875 | Error correcting code with chip kill capability and power saving enhancement A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. Thi... | 08/30/2011 |
| 8010876 | Method of facilitating reliable access of flash memory A method of facilitating reliably accessing flash memory is provided. During the write-in process, the present invention utilizes the steps of coding write-in data to generate extra data, and then generating the first error correction code by performing an error-cor... | 08/30/2011 |
| 8001444 | ECC functional block placement in a multi-channel mass storage device A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffe... | 08/16/2011 |
| 7966547 | Multi-bit error correction scheme in multi-level memory storage system A method, system, and computer software product for operating a collection of memory cells. Memory cells are organized into a group of memory cells, with each memory cell storing a binary multi-bit value delimited by characteristic parameter bands. Two adjacent char... | 06/21/2011 |
| 7966546 | Non-volatile memory with soft bit data transmission for error correction control Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in deco... | 06/21/2011 |
| 7941730 | Memory system A semiconductor memory has a field programmable unit in which logic to inter-convert external signals to be input/output to/from a memory system and internal signals to be input/output to/from a memory cell array is programmed. A program for constructing the logic o... | 05/10/2011 |
| 7925960 | Memory and method for checking reading errors thereof A method for checking reading errors of a memory includes receiving a first data fragment and accordingly generating a first ECC and a first count index; writing the first data fragment, the first ECC and the first count index into a memory; reading the first data f... | 04/12/2011 |
| 7865805 | Multiple bit upset insensitive error detection and correction circuit for field programmable gate array based on static random access memory blocks A method for detecting and correcting bit errors. The method includes the steps of receiving original data, partitioning the memory storage into a first portion and a second portion, storing the original data in the first portion of the memory buffer, modifying the ... | 01/04/2011 |
| 7836380 | Destination indication to aid in posted write buffer loading Embodiments of the invention are generally directed to systems, methods, and apparatuses for a destination indication to aid in posted write buffer loading. In some embodiments, a memory device includes a posted write buffer having a first element and a second eleme... | 11/16/2010 |
| 7805660 | Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program A semiconductor device has multilevel memory cells, each cell storing at least three levels of data each. At least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an N-order of the ... | 09/28/2010 |
| 7752527 | Microcontroller and RAM A microcontroller in which an increase in hardware is suppressed and data correction capability for software error of RAM can be improved is provided. A microcontroller which performs processing according to a program includes a CPU and a RAM for storing data proces... | 07/06/2010 |
| 7681109 | Method of error correction in MBC flash memory A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When ... | 03/16/2010 |
| 7673220 | Flash memory device having single page buffer structure and related programming method A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register c... | 03/02/2010 |
| 7653863 | Data storing method for a non-volatile memory cell array having an error correction code An array of non-volatile memory cells includes a row with N cells and M cells. In a partial-storage step, a datum is stored in a first portion of the N cells of the row. A second portion of the N cells of the row are in an “erase” state. A first error correction... | 01/26/2010 |
| 7644342 | Semiconductor memory device An ECC circuit (103) is located between I/O terminals (1040-1047) and page buffers (1020-1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) for e... | 01/05/2010 |
| 7594158 | Parity error checking and compare using shared logic circuitry in a ternary content addressable memory Methods and apparatus for performing, using smaller, more efficient shared logic circuitry, the parity checking function and the compare function in a mutually exclusive manner in different cycles of a ternary content addressable memory are disclosed. ... | 09/22/2009 |
| 7581154 | Method and apparatus to lower operating voltages for memory arrays using error correcting codes A method comprising running an error correction code on data and storing the data and the result of the error correction code in memory, running an error correction code on the data when it is read from the memory, comparing the results of the error correction codes... | 08/25/2009 |
| 7552378 | Semiconductor device improving error correction processing rate In an exclusive OR circuit (XOR gate) constituting an ECC circuit, the drivability of P channel MOS transistors is set larger than the drivability of N channel MOS transistors. Accordingly, the speed of the logic level of an output node being set to an H level from ... | 06/23/2009 |
| 7523381 | Non-volatile memory with error detection Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a me... | 04/21/2009 |
| 7509561 | Parity checking circuit for continuous checking of the parity of a memory cell A parity checking circuit is designed for continuous parity checking of content-addressable memory cells, and is configured such that during a parity check the number of parity checking steps per data word is the same as the number of bits in the original payload da... | 03/24/2009 |
| 7437651 | System and method for controlling application of an error correction code (ECC) algorithm in a memory subsystem A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to det... | 10/14/2008 |
| 7437597 | Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of E... | 10/14/2008 |
| 7434141 | Network-based memory error decoding system and method A server computer system receives error data including a physical memory address along with configuration data associated with the physical memory address, and may also include error syndrome data. The server computer system includes a memory error decoder component... | 10/07/2008 |
| 7430703 | Error correction for multiple word read An integrated circuit that accesses memory from data lines in multiple word increments having distributed error correction coding circuitry is described. The data lines are selectively coupled to a portion of the memory for a read of data stored in the portion of th... | 09/30/2008 |
| 7428687 | Memory controller method and system compensating for memory cell data losses A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal r... | 09/23/2008 |
| 7428689 | Data memory system and method for transferring data into a data memory A method for transferring data into a data memory using a data protocol is presented. The data memory is an error correction code (ECC) memory or a non-error correction code memory. The data protocol has different frames. When data are written into an ECC memory, th... | 09/23/2008 |
| 7414875 | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structu... | 08/19/2008 |
| 7406649 | Semiconductor memory device and signal processing system The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a ... | 07/29/2008 |
| 7394691 | Semiconductor memory device which prevents destruction of data A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data b... | 07/01/2008 |
| 7395489 | Control system and memory control method executing a detection of an error in a formation in parallel with reading operation A memory control device includes a writing unit writing information to a memory module, a reading unit reading the information from the memory module, an error detecting unit executing a detection of an error in the formation in parallel with the reading operation b... | 07/01/2008 |
| 7392457 | Memory storage device having a nonvolatile memory and memory controller with error check operation mode A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correc... | 06/24/2008 |
