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An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
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| Number | Title | Issue Date |
| 7673219 | Cooperative relay networks using rateless codes A system and method for communicating information in a wireless cooperative relay network of nodes, the nodes including a source, a set of relays, and a destination. The source broadcasts a code word encoded as a data stream using a rateless code. The relays receive... | 03/02/2010 |
| 7428692 | Parallel precoder circuit A parallel precoder circuit executes a differential encoding operation on an n-row parallel input information series, and outputs an n-row parallel output information series, where 2≦n. Output sets of differential encoding operation circuits each of which having a... | 09/23/2008 |
| 7398450 | Parallel precoder circuit A parallel precoder circuit executes an EXOR operation on an n-row parallel input, and outputs an n-row parallel output, where 2≦n. Outputs of EXOR circuits each of which having a largest column number from among EXOR circuits disposed in first to (n−1)th rows b... | 07/08/2008 |
| 7331011 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second... | 02/12/2008 |
| 7320101 | Fast parallel calculation of cyclic redundancy checks Circuits, methods, and apparatus for the fast parallel calculation of CRCs. One embodiment provides a feedforward path that combines common terms to simplify input logic. Common expressions that appear in multiple terms in the feedforward path are implemented using ... | 01/15/2008 |
| 7305593 | Memory mapping for parallel turbo decoding A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transpose... | 12/04/2007 |
| 7299399 | Method and apparatus for parallelly processing data and error correction code in memory A method for parallelly processing data and ECC in the memory and associated apparatus are disclosed. The method includes the following steps: (1) reading the first data, and calculating the first syndrome based on the first data and the first ECC code, (2) correcti... | 11/20/2007 |
| 7284158 | Processor bus for performance monitoring with digests A method for monitoring event occurrences from a plurality of processor units at a centralized location via a dedicated bus coupled between the plurality of processor units and the centralized location. In particular, the method comprises receiving, at the centraliz... | 10/16/2007 |
| 7237175 | Memory circuit When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into mem... | 06/26/2007 |
| 7225387 | Multilevel parallel CRC generation and checking circuit A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic, each CRC circuit having a seed input adapted to receive a seed, a data ... | 05/29/2007 |
| 7206891 | Multi-port memory controller having independent ECC encoders A memory controller system is provided, which includes a plurality of system buses, a multi-port memory controller and a plurality of error correcting code (ECC) encoders. The memory controller has a plurality of system bus ports and a memory port. Each ECC encoder ... | 04/17/2007 |
| 7206962 | High reliability memory subsystem using data error correcting code symbol sliced command repowering A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into symbol slices and each symbol slice is configured to be part of a single... | 04/17/2007 |
| 7181673 | Codeword for use in digital optical media and a method of generating therefor A codeword for use in error correction of digital optical media, the codeword having a plurality of data symbols and a plurality of parity symbols, and includes an augmented channel word which can be read as either a first value or a second alternate value. The augm... | 02/20/2007 |
| 7149932 | Serial communication device and method of carrying out serial communication A serial communication device bridging between a parallel bus and a serial bus, includes (a) a check bit producer which applies an error correcting code to parallel data transmitted through the parallel bus, (b) a parallel-serial converter which converts the paralle... | 12/12/2006 |
| 7137045 | Decoding method and apparatus therefor A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction, indicating in error flags the remaining code words except at least some c... | 11/14/2006 |
| 7076722 | Semiconductor memory device An ECC circuit (103) is located between I/O terminals (1040–1047) and page buffers (1020–1027). The ECC circuit (103) includes a coder configured to generate check bits (ECC) f... | 07/11/2006 |
| 7051265 | Systems and methods of routing data to facilitate error correction Systems and methods are provided for detecting and correcting bit errors in data structures. A data block and/or data structure is partitioned into adjacent bit pair domains, such that a single adjacent bit pair from each memory device is assigned to a given adjacen... | 05/23/2006 |
| 7024616 | Method for encoding/decoding error correcting code, transmitting apparatus and network A client signal having a constant bit rate is segmented every a bytes to create code information blocks. The bit rate of the client signal is increased such that the client signal has the code information block and an empty area comprised of b bytes, and the ratio c... | 04/04/2006 |
| 6986095 | Error correction device For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same time, and until the syndrome calculator detects an error-containing c... | 01/10/2006 |
| 6978343 | Error-correcting content addressable memory A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to c... | 12/20/2005 |
| 6941505 | Data processing system and data processing method A data processing system (1) has an erasable and programmable non-volatile memory (5) and a central processing unit (2). The central processing unit allows only a specified partial storage area (20Ba) of the non-volatile memory to be inte... | 09/06/2005 |
| 6856625 | Apparatus and method of interleaving data to reduce error rate A method and apparatus for reducing the information error rate of a communication network. The apparatus comprises a selector device coupled to a Framer and to an Interleaver. The selector device is configured to receive system information and the Framer is configur... | 02/15/2005 |
| 6820229 | Codeword for use in digital optical media and a method of generation thereof A codeword and a method for generating a codeword is provided. The codeword may be used in error correction of digital optical media and DVDs, the codeword having a plurality of data symbols and a plurality of parity symbols, and includes an augmented channel word w... | 11/16/2004 |
| 6760881 | Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM) A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word includ... | 07/06/2004 |
| 6691276 | Method for detecting and correcting failures in a memory system According to one embodiment, a method is disclosed. The method includes interleaving a first error correction code with a second error correction code to generate a third error correction code that provides chip-kill capabilities for a memory system.... | 02/10/2004 |
| 6684363 | Method for detecting errors on parallel links System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an appropriate CRC value of a message. This determination can ta... | 01/27/2004 |
| 6640326 | Data set recovery by codeword overlay A method for recovering user data from a host device stored on a data storage medium where a said data may become corrupted during a read operation comprises: performing a read operation to read at least one encoded data fragment of said plurality of enco... | 10/28/2003 |
| 6578136 | Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder circuit A disc storage apparatus includes at least one disc having at least one recording surface, at least one head associated with the at least one recording surface for recording data on the at least one recording surface, a decoder circuit which receives code... | 06/10/2003 |
| 6459957 | Programmable smart membranes and methods therefor A programmable smart membrane and methods therefor. The smart membrane conducts an overall function on at least one of a sorting function, a filtering function and an absorbing function of at least one object having an attribute. The smart membrane includ... | 10/01/2002 |
| 6079044 | Method and error correcting code (ECC) apparatus for storing predefined information with ECC in a direct access storage device Apparatus and methods for storing predefined information with error correcting code (ECC) in a direct access storage device are provided. Predetermined information is identified and loaded to an ECC generator for customer data to be read and written. The ... | 06/20/2000 |
| 6052818 | Method and apparatus for ECC bus protection in a computer system with non-parity memory An apparatus and method in which ECC bus protection capability can be generated on a memory card in conjunction with a computer system with a built-in ECC capability to reduce data transmission errors. Data generated by the system is transmitted to the ca... | 04/18/2000 |
| 5978953 | error detection and correction A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and i... | 11/02/1999 |
| 5951708 | Error correction coding and decoding method, and circuit using said method In the coding and decoding of Reed-Solomon codes formed of symbols larger than information symbols, redundant circuitry is eliminated, error detection and correction are preformed using a simple construction, and the reliability of error detection and cor... | 09/14/1999 |
| 5933436 | Error correction/detection circuit and semiconductor memory device using the same An error correction/detection circuit including a syndrome generating circuit for generating a syndrome from information data and check data input in a first cycle; and an error position/size calculating circuit for calculating a position and a size of an... | 08/03/1999 |
| 5896404 | Programmable burst length DRAM A Dynamic Random Access Memory (DRAM) with a burst length programmable as eight (8) or nine (9) bytes. The DRAM array is divided into two or more sub-arrays, with sub-array cells arranged in addressable rows and columns. When the DRAM is programmed in Nor... | 04/20/1999 |
| 5818855 | Galois field multiplier for Reed-Solomon decoder A Reed-Solomon decoder includes an optimized Galois Field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein a first multiplicand of the first multiplier is the magnitude A, and the second multiplicand... | 10/06/1998 |
| 5781568 | Error detection and correction method and apparatus for computer memory An S8ED system is implemented in a memory system to detect single errors involving one or more bits in a byte of subject data, stored in and retrieved from the memory system. Relationships between the subject data and parity data, which are used to detect... | 07/14/1998 |
| 5757823 | Error detection and correction for four-bit-per-chip memory system Advantage is taken of the presence of identity submatrices in a parity check matrix to achieve correction of errors in a single symbol and detection of errors in a single symbol together with a single bit error in another symbol for use in computer memory... | 05/26/1998 |
| 5754563 | Byte-parallel system for implementing reed-solomon error-correcting codes A high-speed byte-parallel pipelined error-correcting system for Reed-Solomon codes includes a parallelized and pipelined encoder and decoder and a feedback failure location system. Encoding is accomplished in a parallel fashion by multiplying message wor... | 05/19/1998 |
| 5491703 | Cam with additional row cells connected to match line A method of accessing a content addressable memory having a plurality of RAM cells connected in an array of rows and columns, each row having a plurality of cells for storing a data word, at least one additional cell for storing a checking bit and a match... | 02/13/1996 |
