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"I hate what they've done to my child...I would never let my own children watch it. "
Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 8176389 | Decoder device and method for decoding data stored in storage medium A decoder device includes: a decoder that decodes data stored in a storage medium by performing error correction on the data, the error correction being capable of correcting code error and code erasure included in the data; a memory that stores a history of an addr... | 05/08/2012 |
| 8127205 | Error correction code generation method and memory control device A correct error correction code can be generated even if a RAM error occurs before writing store data in cache memory (RAM) after confirming that cache line data for storage includes no errors. Before writing the store data, cache line data for storage is stored in ... | 02/28/2012 |
| 8103940 | Programming error correction code into a solid state memory device with varying bits per cell Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individua... | 01/24/2012 |
| 8042023 | Memory system with cyclic redundancy check A memory system, with a memory controller and a memory module, is configured to transfer error securing data and address signals within signal frames between the memory controller and the memory module. The memory system includes: an address register configured to p... | 10/18/2011 |
| 8006166 | Programming error correction code into a solid state memory device with varying bits per cell Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individua... | 08/23/2011 |
| 7971124 | Apparatus and method for distinguishing single bit errors in memory modules An apparatus, system, and method are disclosed for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in memory. The correctable bit error is correctable using error-correcting code (“ECC”). A comparison... | 06/28/2011 |
| 7941729 | Data storage device and error processing method in its read processing Embodiments in accordance with the present invention help a disk drive to effectively cope with a data address mark detection error. In one embodiment, a data sector is provided with plural data address marks and an read/write (RW) channel reads out the data sector ... | 05/10/2011 |
| 7810016 | Semiconductor storage device equipped with ECC function A semiconductor memory device includes a memory cell array, an ECC (error correction code) circuit and a decision circuit. The ECC circuit calculates an error correction code for write data to be written in the memory cell array. The decision circuit invalidates the... | 10/05/2010 |
| 7774685 | HDD sector format with reduced vulnerability to defects and burst errors Modified HDD sector formats have multiple sets of preamble data. The preambles are well separated so that any defect long enough to wipe out both preambles would also overwhelm the ECC. ... | 08/10/2010 |
| 7761774 | High speed CAM lookup using stored encoded key The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged... | 07/20/2010 |
| 7747927 | Method for adapting a memory system to operate with a legacy host originally designed to operate with a different memory system A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was or... | 06/29/2010 |
| 7689891 | Method and system for handling stuck bits in cache directories A method of handling a stuck bit in a directory of a cache memory which detects an error in a stored tag having an address field, a state field and an error-correction field, determines that the error is associated with a stuck bit of the directory member, marks the... | 03/30/2010 |
| 7631245 | NAND flash memory controller exporting a NAND interface A NAND controller for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a con... | 12/08/2009 |
| 7543217 | Method of determining suitability of a recording medium for being recorded to and/or reproduced from by an apparatus Suitability of a recording medium for being recorded to and/or reproduced from by an apparatus is determined. Address information is read from a recording medium having at least a first area in which data is recordable, a second area, and a third area. The second ar... | 06/02/2009 |
| 7533323 | Adaptive archival format Data are stored on a random-access storage medium. A user set of data is received. The user set of data is mapped to multiple frames. For each frame, error-correction bytes are generated over the data mapped to that frame. In addition, the data mapped to that frame ... | 05/12/2009 |
| 7421642 | Method and apparatus for error detection The present invention is an error detection and correction scheme that enables the use of Horner's algorithm for the computation of EDC syndromes from the computed error pattern. Specifically, “transformed” EDC syndromes are computed during the read back of data... | 09/02/2008 |
| 7418645 | Error correction/detection code adjustment for known data pattern substitution Techniques for updating cyclic redundancy check (CRC) bytes for data sectors that have been reassigned to a new logical block address (LBA) are provided. The entire set of CRC check bytes is not recalculated each time that a data sector is reassigned to a new LBA. I... | 08/26/2008 |
| 7404137 | Method and related apparatus for performing error checking-correcting A method and related apparatus for performing error checking-correcting (ECC). The method divides a memory space provided by a memory into an ECC range and a non-ECC range. When data is read or written, the method determines the address of data is within the ECC ran... | 07/22/2008 |
| 7398449 | Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are con... | 07/08/2008 |
| 7395489 | Control system and memory control method executing a detection of an error in a formation in parallel with reading operation A memory control device includes a writing unit writing information to a memory module, a reading unit reading the information from the memory module, an error detecting unit executing a detection of an error in the formation in parallel with the reading operation b... | 07/01/2008 |
| 7392347 | Systems and methods for buffering data between a coherency cache controller and memory In one embodiment, the present invention is directed to a system processing memory transaction requests. The system includes a controller for storing and retrieving cache lines and a buffer communicatively coupled to the controller and at least one bus. The controll... | 06/24/2008 |
| 7376887 | Method for fast ECC memory testing by software including ECC check byte The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or mu... | 05/20/2008 |
| 7366829 | TLB tag parity checking without CAM read An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag ... | 04/29/2008 |
| 7363533 | High reliability memory module with a fault tolerant address and command bus A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit ser... | 04/22/2008 |
| 7353433 | Poisoned error signaling for proactive OS recovery Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered. ... | 04/01/2008 |
| 7350133 | Error correction encoding apparatus and method and error correction decoding apparatus and method An error correction encoding method including generating error correction code data, which is a predetermined number of bytes long, by error-correction-encoding user data in a predetermined manner; generating burst indicator subcode data, which is a predetermined nu... | 03/25/2008 |
| 7337371 | Method and apparatus to handle parity errors in flow control channels Methods, software and systems for handling parity errors in flow control channels are presented. A network processor is provided having a flow control message First In First Out (FIFO) buffer and wherein the FIFO buffer includes a parity field. The network processor... | 02/26/2008 |
| 7337352 | Cache entry error-connecting code (ECC) based at least on cache entry data and memory address Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry in... | 02/26/2008 |
| 7333516 | Interface for synchronous data transfer between domains clocked at different frequencies The present invention provides an interface and method for synchronous data transfer between domains clocked at different frequencies. The interface includes a first latch for receiving data from a first domain clocked at one frequency when the first latch is select... | 02/19/2008 |
| 7320086 | Error indication in a raid memory system A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory mod... | 01/15/2008 |
| 7304873 | Method for on-the-fly error correction in a content addressable memory (CAM) and device therefor A CAM system (200) can include a number of entries (202-0 to 202-3) having one portion for storing a data value (e.g., E1) and another portion for storing a replicated data value (E1(REP)). For on-the-fly error correc... | 12/04/2007 |
| 7304875 | Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in sel... | 12/04/2007 |
| 7293221 | Methods and systems for detecting memory address transfer errors in an address bus A method for detecting transfer errors in an address bus is provided. In this method, a first address parity is generated using a memory address. Next, at least two data error-correction-code (ECC) check bits are scrambled using the first address parity. Subsequentl... | 11/06/2007 |
| 7293139 | Disk array system generating a data guarantee code on data transferring To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/... | 11/06/2007 |
| 7284183 | Method and apparatus for decoding multiword information A method for decoding multiword information comprises steps (a) to (h). In step (a), a multiword information cluster including high protective words and low protective words is provided, wherein the multiword information, high protective words and low protective wor... | 10/16/2007 |
| 7281193 | Method and apparatus for decoding multiword information A method for decoding multiword information comprises multiple steps. In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protect... | 10/09/2007 |
| 7277586 | Images combination processing system, images combination processing method, and images combination processing program An images combination processing system has a CCD or an imaging element including CCDs for picking up an image, compression processing portions for applying JPEG compression, etc. to image data in respective areas into which a picked-up image is divided, a buffer fo... | 10/02/2007 |
| 7275202 | Method, system and program product for autonomous error recovery for memory devices An autonomous error recovery approach is provided for a memory device of a computing system. In response to a request for data, addressed data and associated control information of the memory device are tested for error. If error is detected, the contents of an addr... | 09/25/2007 |
| 7269776 | Apparatus and method for performing bit de-collection in a communication system using a high speed downlink packet access (HSDPA) scheme An apparatus and a method for performing a bit de-collection according to a hybrid automatic retransmission request are disclosed. The apparatus includes a column counter for increasing one column every four bits and outputting a position of a current column in resp... | 09/11/2007 |
| 7266432 | Method of diagnosing an electronic control unit An electronic control unit and a method of diagnosing an electronic control unit on a vehicle are provided. The method includes the steps of storing in memory information on variables to collect, selecting a trigger, monitoring for a predetermined event, activating ... | 09/04/2007 |
