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Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 8161356 | Systems, methods, and apparatuses to save memory self-refresh power Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check m... | 04/17/2012 |
| 8156404 | L2 ECC implementation One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bi... | 04/10/2012 |
| 8127203 | Method, data processing apparatus and wireless device Embodiments of the invention relate generally to a method, to a data processing apparatus and to a wireless device. In an embodiment of the invention a data processing apparatus is provided. The data processing apparatus may include a chip-integrated unit to select ... | 02/28/2012 |
| 8127204 | Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to ... | 02/28/2012 |
| 8122322 | System and method of storing reliability data Systems and methods of storing error correction data are provided. A method may include storing data at a first memory having a first non-volatile memory type. The method may also include determining error correction data related to the stored data. The method may f... | 02/21/2012 |
| 8103939 | Storage system and data storage method The storage system includes a first memory device configured to store data sent from a host system, a first memory device controller configured to control read/write access of the data from/to the first memory device, an arithmetic circuit unit configured to calcula... | 01/24/2012 |
| 8091008 | Data read-out circuit in semiconductor memory device and method of data reading in semiconductor memory device A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the s... | 01/03/2012 |
| 8015471 | Symbol rate hardware accelerator A hardware accelerator includes a first buffer, a second buffer, address generator(s), a translation read-only memory (ROM), a cyclic redundancy check (CRC) generator, a convolutional encoder and a controller. The first and second buffers store information bits. The... | 09/06/2011 |
| 7984360 | Avoiding errors in a flash memory by using substitution transformations To store an input string of M N-tuples of bits, a substitution transformation is selected in accordance with the input string and is applied to the input string to provide a transformed string of M N-tuples of bits. M or more memory cells are programmed to represent... | 07/19/2011 |
| 7937646 | Reading method and apparatus for an information recording medium and spare area allocation thereof An information recording medium reading method is provided. The information recording medium has a user data area for recording data and at Least one spare area for recording replacements for defects of the user data area. The method includes steps of sequentially r... | 05/03/2011 |
| 7861140 | Memory system including asymmetric high-speed differential memory interconnect A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controll... | 12/28/2010 |
| 7856588 | Data allocation in memory chips In one embodiment, a memory device comprises a first partition to divide the memory device into a first segment to hold a first data block and a second segment to hold a second data block, and a codeword in a single internal word of the memory device. ... | 12/21/2010 |
| 7840876 | Power savings for memory with error correction mode The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal... | 11/23/2010 |
| 7814396 | Apparatus and method for checking an error recognition functionality of a memory circuit Checking an error recognition functionality of a memory circuit including a memory that stores a datum, and a check value circuit that executes the error recognition functionality, is performed by a monitoring circuit. The memory circuit provides the datum to the ch... | 10/12/2010 |
| 7805658 | DRAM Cache with on-demand reload Embodiments include a DRAM cache structure, associated circuits and method of operations suitable for use with high-speed caches. The DRAM caches do not require regular refresh of its data and hence the refresh blank-out period and refresh power are eliminated, thus... | 09/28/2010 |
| 7783957 | Apparatus for implementing enhanced vertical ECC storage in a dynamic random access memory A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that mu... | 08/24/2010 |
| 7774684 | Reliability, availability, and serviceability in a memory device Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store... | 08/10/2010 |
| 7761773 | Semiconductor device including a unique identifier and error correction code A semiconductor device includes a plurality of laser fuses and each laser fuse represents a bit of data. A first set of the plurality of laser fuses represents a unique identifier that corresponds to the semiconductor device. Also, a second set of the plurality of l... | 07/20/2010 |
| 7721182 | Soft error protection in individual memory devices Techniques are disclosed for minimizing the effects of soft errors associated with memory devices that are individually accessible. By way of example, a method of organizing a column in a memory array of a memory device protected by an error correction code comprise... | 05/18/2010 |
| 7716555 | Data backup method and memory device Disclosed herein is a memory device which comprises a nonvolatile memory having first and second areas and a controller that stores backup data along with checksum data alternately in the first and second areas. In the first and second areas, data storing areas and ... | 05/11/2010 |
| 7689890 | System and method for handling write commands to prevent corrupted parity information in a storage array An architecture and method for executing write commands in a storage array is disclosed. The data strips of the data stripes of the storage array each include a parity check bit. The parity strip of each stripe includes a plurality of parity check bits, each of whic... | 03/30/2010 |
| 7681107 | Semiconductor device A semiconductor having an internal memory of the present invention comprises a first memory copying and holding a data held in a storage device; a second memory holding a check code of the data held in the first memory, and being constantly supplied with a source vo... | 03/16/2010 |
| 7650558 | Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type for both error check and non-error check systems. In an embodiment, a memory device is capable of operating in an error check mode and in a non-er... | 01/19/2010 |
| 7640481 | Integrated circuit having multiple modes of operation A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include first circuitry and second circuitry. The first circuitry may be capable of performing at least one operation includi... | 12/29/2009 |
| 7634708 | Relocatable storage protect keys for system main memory Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can b... | 12/15/2009 |
| 7624329 | Programming a memory device having error correction logic Methods and apparatus for programming a non-volatile memory array comprising addressable units are provided. The addressable units are configured to store at least a main portion and an error correction portion. An exemplary method for programming the non-volatile m... | 11/24/2009 |
| 7613982 | Data processing apparatus and method for flash memory A data processing apparatus and method for a flash memory, which make it easy to determine whether data stored in the flash memory is valid, are provided. The data processing apparatus includes a user request unit which issues a request for performing a data operati... | 11/03/2009 |
| 7603610 | Coding a video data stream with unequal error protection based activity A method adapted to detect the activity of individual partitions within a packetized frame. The method provides for the encoding of those portions of the data stream having higher activity more than those portions having less activity. This enables a protection diff... | 10/13/2009 |
| 7565598 | Error correction for disk storage media Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by in... | 07/21/2009 |
| 7539923 | Circuit and method of transmitting a block of data A circuit for transmitting a block of data is disclosed. The circuit comprises a memory array having a plurality of memory locations coupled to receive data; a first data source coupled to the memory array, wherein data from the first data source is stored at sequen... | 05/26/2009 |
| 7512864 | System and method of accessing non-volatile computer memory A system and method for organizing a non-volatile memory is provided. The system includes a non-volatile memory with a first data region and a first redundant memory area associated with the first data region. The first redundant memory area includes a first portion... | 03/31/2009 |
| 7464321 | Apparatus and method to transfer information from a first information storage and retrieval system to a second information storage and retrieval system A method is disclosed to transfer information from a first information storage and retrieval system to a second information storage and retrieval system. The method provides a first information storage and retrieval system comprising a first track size and a plurali... | 12/09/2008 |
| 7464322 | System and method for detecting write errors in a storage device A system for detecting write errors in a storage device is disclosed. The system includes a storage device having means for storing one or more data blocks in a storage group. The storage group includes one or more data blocks and a check block having one of the gro... | 12/09/2008 |
| 7451380 | Method for implementing enhanced vertical ECC storage in a dynamic random access memory A method and apparatus are provided for implementing enhanced vertical ECC storage in a dynamic random access memory. A dynamic random access memory (DRAM) is split into a plurality of groups. Each group resides inside a DRAM row address strobe (RAS) page so that mu... | 11/11/2008 |
| 7447976 | Data transfer apparatus A data transfer apparatus improving data transfer rate regardless of the original transfer mode in a USB interface is disclosed. A computer includes a bulk packet generation unit and an isochronous packet transmission unit. The bulk packet generation unit generates ... | 11/04/2008 |
| 7428690 | Packet communication apparatus A packet communication apparatus, which includes a CPU, a memory, and a packet communication circuit, acts as an interface between a network-connected controlled object and a network terminal that remotely monitors and controls the controlled object, and transmits a... | 09/23/2008 |
| 7401228 | Method for transmitting data, apparatus for recording data, medium for recording data, and apparatus for reproducing data A data transmitting method, a data recording apparatus, a data record medium and a data reproducing apparatus are provided to disallow the encryption to be easily decoded and keep the secrecy of key information higher. The data transmitting apparatus includes an err... | 07/15/2008 |
| 7398351 | Method and system for controlling access to data of a tape data storage medium using encryption/decryption of metadata A method, system, and machine-readable medium for controlling access to data of a tape data storage medium are disclosed. In accordance with one embodiment, a method is provided which comprises conveying data access control metadata from a tape cartridge comprising ... | 07/08/2008 |
| 7380198 | System and method for detecting write errors in a storage device A system for detecting write errors in a storage device is disclosed. The system comprises a storage device; within the storage device, means for storing one or more data blocks in a storage group, the storage group comprising the one or more data blocks and a check... | 05/27/2008 |
| 7373564 | Semiconductor memory A normal write data selection circuit operates in the normal operation mode, and thus outputs data received through external data terminals to any one of regular cell arrays selected according to an address. A test write control circuit operates in the test mode, an... | 05/13/2008 |
