Bizarre Patents
Pet Toilet-Like Water Disk and Food Storage
One pet-friendly inventor patented "a device for watering pets, e.g., a dog or cat." The device, he helpfully noted, "has the general shape of a toilet."
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| Number | Title | Issue Date |
| 8122321 | Methods of data handling Methods of data handling include receiving data having a previously-generated error correction code and generating one or more error correction codes for the data, with each error correction code corresponding to the data having one or more particular bits of the da... | 02/21/2012 |
| 8112693 | Error control code apparatuses and methods of using the same An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining ... | 02/07/2012 |
| 8032816 | Apparatus and method for distinguishing temporary and permanent errors in memory modules An apparatus and method for distinguishing correctable bit errors in memory. A bit error detection module detects a correctable bit error in a memory in response to a READ operation. The correctable bit error is correctable using error-correcting code. The READ oper... | 10/04/2011 |
| 7987408 | Data buffering method In a data processing and buffering method, at least one read cycles are asserted to obtain at least one data, respectively, wherein each of the data includes at least one sub data and each data is specified with an address pointer and an enable bit array. When a cer... | 07/26/2011 |
| 7917832 | Apparatus for improving data access reliability of flash memory An apparatus for improving the data access reliability of flash memory is provided, including an instruction register, an address register, a flash memory control circuit, a data register, an encoder, an error correction code (ECC) generator, a signal converter, a c... | 03/29/2011 |
| 7774683 | Erasure pointer error correction Improved memory devices, circuitry, and data methods are described that facilitate the detection and correction of data in memory systems or devices in combination with a stored record of known flaws, errors, or questionable data bits of a read memory row or block t... | 08/10/2010 |
| 7752526 | Nonvolatile memory apparatus and data processing system The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer ... | 07/06/2010 |
| 7360039 | Arrangements storing different versions of a set of data in separate memory areas and method for updating a set of data in a memory Computer-readable medium storing a data structure for supporting persistant storage of a set of data, the data structure including: (a) at least an oldest version of the set of data in a first memory area the first memory area including at least one first tag for un... | 04/15/2008 |
| 7353433 | Poisoned error signaling for proactive OS recovery Use of data poisoning techniques may permit proactive operating system recovery without needing to always bringing down the operating system when uncorrectable errors are encountered. ... | 04/01/2008 |
| 7331011 | Semiconductor integrated circuit device A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second... | 02/12/2008 |
| 7331004 | Data storage system analyzer having self reset A transmitter board transmits a copy of signals in a system being analyzed by the system analyzer. The copy of such signals comprises serial data in a low byte serial link and in a high byte serial link. The signals include special characters interspersed in a patte... | 02/12/2008 |
| 7328395 | Iterative Reed-Solomon error-correction decoding Systems and methods are provided to correct errors occurring in a decision-codeword that is generated by a detector. A decoder determines whether errors in the decision-codeword are of a degree that exceeds the correction capability of a Reed-Solomon error-correctio... | 02/05/2008 |
| 7322003 | Information storage device A control unit transfers user data and an ECC that are read from a magnetic disk and stored in an FIFO to a data buffer. An erasure position movement control unit shifts an erasure start position from a predetermined initial value at predetermined intervals of erasu... | 01/22/2008 |
| 7310765 | Method and apparatus for checking read errors with two cyclic redundancy check stages A system for detecting errors in received input data includes a first error detection circuit. The first error detection circuit is configured to receive the input data. The input data includes at least one of data and data with errors. The first error detection cir... | 12/18/2007 |
| 7290197 | Correcting data using redundancy blocks Errors in data retrieved from a storage medium are corrected by retrieving a plurality of data blocks and a plurality of redundancy blocks associated with the plurality of data blocks from the storage medium. One or more data blocks retrieved from the storage medium... | 10/30/2007 |
| 7289669 | Data managing method and apparatus for providing divisional data A data managing device includes divisional decoded data storage for at least storing divisional data obtained by dividing data of a predetermined unit; and priority order management for at least determining the priority as to erasure of the stored divisional data by... | 10/30/2007 |
| 7284164 | Method and apparatus for error correction of read data in a disk drive A disk drive comprising a read channel including a decoder and an EP unit, and a disk controller including an error correction unit is disclosed. The EP unit generates error positional information showing an error position among data output from the decoder. The dis... | 10/16/2007 |
| 7277498 | Mapping method of code word with QAM modulation In the code word mapping operation of a radio communication system, mapping patterns are provided for different S/N ratios, the code word bits produced from a coder are not equally assigned to multi-level modulation bits, but weighted according to the resistance of ... | 10/02/2007 |
| 7275135 | Hardware updated metadata for non-volatile mass storage cache An apparatus and method to de-allocate data in a cache memory is disclosed. Using a clock that has a predetermined number of periods, the invention provides a usage timeframe information to approximate the usage information. The de-allocation decisions can then be m... | 09/25/2007 |
| 7266748 | Method and apparatus for correcting C1/PI word errors using error locations detected by EFM/EFM+ decoding A method and system for error correcting C1/PI words using error locations detected by EFM/EFM+ decoder are provided. The method for channel decoding and error correcting includes: (a) setting up a channel code; (b) producing demodulated data including inform... | 09/04/2007 |
| 7263631 | Soft error detection and recovery A logic circuit is provided that implements soft error detection and recovery for protecting the logic circuit from the negative effects of soft errors caused by single event upsets. The logic circuit may include a configurable processing module, an input buffer, an... | 08/28/2007 |
| 7260848 | Hardened extensible firmware framework A method for hardening an extensible firmware framework and system in which the framework is implemented. In accordance with the method, a resource access policy that defines rules to allow or disallow access to designated system resources, such as memory and I/O, i... | 08/21/2007 |
| 7243297 | Method for bit recovery in an asymmetric data channel A demodulator performs bit recovery in an asymmetric data channel, such as an optical recording media, by detecting runlength violations prior to demodulation, and correcting the detected runlength violations prior to the demodulation. ... | 07/10/2007 |
| 7237173 | Recording and reproducing apparatus, signal decoding circuit, error correction method and iterative decoder A recording and reproducing apparatus having an ECC-less error correction function, includes an erasure detector generating an erasure flag indicating erasure of a read signal; and an iterative decoder having two soft-in/soft-out (SISO) decoders, i.e., an inner deco... | 06/26/2007 |
| 7231580 | Nonvolatile memory apparatus and data processing system The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer ... | 06/12/2007 |
| 7225390 | Semiconductor memory device provided with error correcting code circuitry A semiconductor synchronous dynamic random access memory (SDRAM) device capable of correcting bits having a low error rate in a Pause Refresh Tail distribution and of reducing a data holding current by lengthening a refresh period so that the refresh period exceeds ... | 05/29/2007 |
| 7213191 | System and method for securely storing data in a memory A system for securely storing data in a memory includes a memory (1) and a CPU (Central Processing Unit) (2). The memory is divided into a plurality of fixed-size blocks (10) for storing data. Each block includes a plurality of data pages (10... | 05/01/2007 |
| 7206962 | High reliability memory subsystem using data error correcting code symbol sliced command repowering A memory subsystem comprising: a command register in operable communication with a plurality of memory devices via a plurality of command buses. The plurality of memory devices is arranged into symbol slices and each symbol slice is configured to be part of a single... | 04/17/2007 |
| 7200042 | Method and circuit arrangement for reading from a flash/EEPROM memory cell The invention is based on a method for reading out the content of a flash/EEPROM memory cell, in which a read current flowing via a read-out path with a memory cell having a memory transistor is compared with a reference current flowing via at least one read-out pat... | 04/03/2007 |
| 7188294 | High-efficiency error detection and/or correction code A method for determining r error detection bits of a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix. The parity control matrix in... | 03/06/2007 |
| 7181669 | Device and method for block code error correction A device and method for block code error correction. The device includes a block code input unit, an erasing address table, an error table and a decoder. The block code input unit is used to input a block code. The erasing address table and the error table have a pl... | 02/20/2007 |
| 7171607 | Apparatus and method for verifying erasure correction function When a special write command from a host is executed, switching is performed so that the data designated by the command will not be input to an ECC generator. In accordance with an erasure pointer setting command from the host, a programmable erasure pointer generat... | 01/30/2007 |
| 7171591 | Method and apparatus for encoding special uncorrectable errors in an error correction code An error correction code for encoding the presence of a special uncorrectable error as well as its type. In the encoder, modification logic modifies the regular data symbols to indicate the type of special uncorrectable error. The encoder appends to the regular data... | 01/30/2007 |
| 7171594 | Pausing a transfer of data Methods and systems are provided for transferring data and for pausing the transfer of data when certain conditions are met. In one embodiment, an error correcting code (ECC) encoder/decoder reads a codeword from a data storage device and decodes the codeword. The E... | 01/30/2007 |
| 7168026 | Method and apparatus for preservation of failure state in a read destructive memory One aspect of the invention provides a novel scheme to preserve the failure state of a memory location. According to one embodiment, the data is read from a memory location in a read-destructive memory device. If the data is found to be valid (uncorrupted) it is wri... | 01/23/2007 |
| 7165195 | Method, system, and apparatus for bit error capture and analysis for serial interfaces An apparatus and method to facilitate validation and/or test of serial interfaces by analyzing error event types based at least in part on a code-stamp, compare engine logic and a memory for error capture. ... | 01/16/2007 |
| 7142021 | Data inversion circuits having a bypass mode of operation and methods of operating the same An integrated circuit device includes a data inversion circuit configured to support an inversion mode of operation. The inversion mode of operation inverts selected ones of a plurality of N-bit words received in consecutive sequence at inputs thereof. The data inve... | 11/28/2006 |
| 7120850 | Low-cost methods and devices for the decoding of product cases A method of decoding product codes is disclosed, in which the symbols of each codeword may be placed in a table comprising n2 rows and n1 columns, such that the symbols constituting each row form a permitted word of length n1 accordi... | 10/10/2006 |
| 7117420 | Construction of an optimized SEC-DED code and logic for soft errors in semiconductor memories An apparatus for memory error control coding comprising a first circuit and a second circuit. The first circuit may be configured to generate a multi-bit digital syndrome signal in response to a read data signal and a read parity signal. The second circuit may be co... | 10/03/2006 |
| 7117428 | Redundancy register architecture for soft-error tolerance and methods of making the same A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whet... | 10/03/2006 |
