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| Number | Title | Issue Date |
| 8190973 | Apparatus and method for error correction of data values in a storage device A data processing apparatus is provided in which a processing unit, by means of a read access request, accesses a storage device which stores data values and error data associated with those data values. When the processing unit accesses a data value in the storage ... | 05/29/2012 |
| 8185802 | Data memory system A data memory system includes a nonvolatile memory cell array which includes a plurality of memory cells, a page adjacently formed by the plurality of memory cells being collectively erased in the nonvolatile memory cell, at least binary pieces of digital data of â€... | 05/22/2012 |
| 8176388 | System and method for soft error scrubbing A data processing system includes a memory configured to store data in a plurality of addressable storage spaces thereof, wherein the memory includes a first data port and a second data port, a first functional block configured to access the memory via the first dat... | 05/08/2012 |
| 8171378 | Flash memory system having encrypted error correction code and encryption method for flash memory system A flash memory system includes a flash memory for storing input data, and a memory controller controlling the flash memory, wherein the memory controller generates a first error correction code corresponding to the input data, and encrypts the first error correction... | 05/01/2012 |
| 8156403 | Combined distortion estimation and error correction coding for memory devices A method for operating a memory device (24) includes encoding data using an Error Correction Code (ECC) and storing the encoded data as first analog values in respective analog memory cells (32) of the memory device. After storing the encoded data, sec... | 04/10/2012 |
| 8151167 | Program processing device and program processing method A program processing device has a non-volatile storage, a volatile storage and a controller. The controller has a detector that detects a bit flip in the program, the variable data, and the constant data in the volatile storage, a constant recovery unit that, when t... | 04/03/2012 |
| 8145941 | Detection and correction of block-level data corruption in fault-tolerant data-storage systems Various embodiments of the present invention provide fault-tolerant, redundancy-based data-storage systems that rely on disk-controller-implemented error detection and error correction, at the disk-block level, and RAID-controller-implemented data-redundancy methods... | 03/27/2012 |
| 8140939 | Flash error correction A data processing device for detecting and correcting data errors of a re-writable memory via an error correction algorithm. In one embodiment, the data processing device includes a coding unit implemented in hardware and an error correction unit implemented in soft... | 03/20/2012 |
| 8140940 | Method and apparatus for controlling memory A memory control apparatus includes a reading unit, an inserting unit, an identifying unit, a determining unit, and an outputting unit. The reading unit reads data from the memory. The inserting unit inserts a dummy error at an insertion position in the data thereby... | 03/20/2012 |
| 8140941 | Data receiving apparatus, data receiving method, and computer-readable recording medium A data receiving method according to the present invention includes: storing received packets in a data storing unit; storing, in a data-storage-information storing unit, information indicating data portions are stored; specifying FEC parameters of column FEC packet... | 03/20/2012 |
| 8127202 | Use of alternative value in cell detection A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage represen... | 02/28/2012 |
| 8127201 | Nonvolatile semiconductor memory and method of access evaluation to the same A nonvolatile memory includes a memory cell array having multiple memory cells, a read-out circuit outputting data stored in the memory cell array asynchronously in response to an input address signal, a selection circuit outputting a selection signal for selecting ... | 02/28/2012 |
| 8117519 | Memory apparatus and method using erasure error correction to reduce power consumption An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells ... | 02/14/2012 |
| 8108755 | Method and apparatus of correcting error data caused by charge loss within non-volatile memory device Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting... | 01/31/2012 |
| 8103938 | Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the q... | 01/24/2012 |
| 8095853 | Digital memory with fine grain write operation Methods, systems, and apparatus for operating digital memory including determining, by a controller, a bit to be written to the digital memory and writing, by the controller, the bit. The bit may be part of a data word comprising a plurality of bits and both the det... | 01/10/2012 |
| 8078940 | Non-volatile semiconductor memory device A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculatio... | 12/13/2011 |
| 8042022 | Method, system, and apparatus for distributed decoding during prolonged refresh Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh oper... | 10/18/2011 |
| 8032815 | Semiconductor memory device A semiconductor memory device configured to execute a standby operation for saving power during standby, and including a memory cell array including plural memory cells arranged at intersections of bit lines and word lines and storing cell data. A redundant memory c... | 10/04/2011 |
| 8020072 | Method and apparatus for correcting data errors The illustrative embodiments provide a computer implemented method and an apparatus for correcting data errors. An error correction unit receives data from a register. Responsive to receiving the data from the register, the error correction unit determines whether a... | 09/13/2011 |
| 7987407 | Handling of hard errors in a cache of a data processing apparatus A data processor includes a cache record error storage and a hard error storage having at least one record error storage and at least one hard error record, respectively, both for keeping track of errors detected when accessing cache records. When an error is first ... | 07/26/2011 |
| 7984359 | Correction of data errors in a memory buffer Methods, circuits, and disk drive that correct errors in data that is temporarily stored in a memory buffer are disclosed. An error detection code and an error correction code are generated for data. The data, the error detection code, and the error correction code ... | 07/19/2011 |
| 7945841 | System and method for continuous logging of correctable errors without rebooting In some embodiments, the invention involves a system and method to continuously log correctable errors without rebooting by changing the granularity of the error detection and logging mechanism. A mask register is used to identify which errors are to be logged. Each... | 05/17/2011 |
| 7900120 | Memory system and method using ECC with flag bit to identify modified data A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller a... | 03/01/2011 |
| 7895502 | Error control coding methods for memories with subline accesses A two-level error control protocol detects errors on the subline level and corrects errors using the codeword for the entire line. This enables a system to read small pieces of coded data and check for errors before accepting them, and in case errors are detected, t... | 02/22/2011 |
| 7890838 | Storage apparatus having nonvolatile storage module According to one embodiment, a storage apparatus includes a first nonvolatile storage module, a second nonvolatile storage module, and an error checking and correction module. The first nonvolatile storage module undergoes a destructive read when data is read from i... | 02/15/2011 |
| 7877669 | Non-volatile memory with error detection Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a me... | 01/25/2011 |
| 7877668 | Memory access system When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the me... | 01/25/2011 |
| 7844880 | Error correction for flash memory Systems and methods are disclosed to detect and correct errors in a flash memory using an error correction cache that provides error correction information by accessing data from a physical block number (PBN) of the flash memory; and if a data error occurred, applyi... | 11/30/2010 |
| 7823046 | Semiconductor device A semiconductor device has a memory section including a first and second memory cell storing a data bit and error correcting bit, respectively. An error correcting section outputs a data signal containing an error-corrected data bit, using the error correcting bit a... | 10/26/2010 |
| 7774682 | Processing configuration data frames In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least othe... | 08/10/2010 |
| 7676728 | Apparatus and method for memory asynchronous atomic read-correct-write operation A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows bein... | 03/09/2010 |
| 7594157 | Memory system with backup circuit and programming method Provided are a memory system and a program method. The memory system includes a flash memory and a memory controller. The flash memory stores first bit data and then stores second bit data in a multi-level memory cell. The memory controller includes a buffer memory ... | 09/22/2009 |
| 7496823 | Hardware based memory scrubbing This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to de... | 02/24/2009 |
| 7420967 | Method and system for data transfer The objective of the invention is to provide a type of data transfer system for generating plural timing signals, etc. for any device. Data transfer system A transfers plural data blocks received with one input channel to plural output channels. Each data block cont... | 09/02/2008 |
| 7414875 | Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structu... | 08/19/2008 |
| 7409585 | Automatic media repair after read failure due to media error A system and method are provided for a storage device that performs automatic media repair so that, after a media error is encountered, subsequent write operations are completed on a known good sector while read operations from the repaired sector are induced to fai... | 08/05/2008 |
| 7404118 | Memory error analysis for determining potentially faulty memory components Accordingly, there has been described a computer system with a plurality of memory components where individual bits from multiple words are distributed among the memory components. An error analyzer is operable to identify a memory component as potentially faulty by... | 07/22/2008 |
| 7401267 | Program failure recovery Methods and apparatus are provided. A method of operating a memory device includes detecting a programming failure at a first location of a memory array, preserving data within the memory device when the program failure is detected, programming a second location of ... | 07/15/2008 |
| 7398439 | Semiconductor device with memory and method for memory test A semiconductor device is disclosed which includes a data memory which stores data and a code memory which stores an ECC code corresponding to the data. The semiconductor device includes an ECC unit which outputs, to the data memory as the data, a test pattern requi... | 07/08/2008 |
